Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops

In this work, a monotonic increasing piecewise-linear (PWL) memristor-based proportional-integral (PI) controller is analyzed. A periodic rectangular pulse current source is used as the input signal, and the proportionality constant of the PWL memristor-based PI controller is varied according to the amount of charge that passes through the memristor. A circuit is proposed to achieve zero net-charge injection for the memristor so that the memristance of the PWL memristor can be varied in the subsequent period. The proposed PWL memristor-based PI controller can be used in the design of the loop filter for the charge-pump phase-locked loop for achieving a faster dynamical response from an unlocked state to a locked state compared to conventional fixed proportional constant PI controllers.     

Synchronization and chaos in coupled memristor-based FitzHugh-Nagumo circuits with memristor synapse

The memristor has drawn a significant interest in the fields of neuromorphic circuits because the nanoscale memristor is a strong candidate to become the critical element of novel ultra-high density low-power non-volatile memories. In the present paper, we focus on networks of FitzHugh-Nagumo neuron circuits employing memristor. First, we build the memristor-based circuit of FitzHugh-Nagumo model. The details of the chaotic phenomena of the memristor-based FitzHugh-Nagumo circuit under external stimuli have been found with use of computer simulations, i.e., we have numerically calculated waveform diagrams, phase portraits, Lyapunov exponents and bifurcation diagram. And we also confirm these results of theoretical analyses and numerical calculations by circuit simulation experiments of the actual analog circuit realization using Multisim modeling. Then the synchronization of coupled memristor-based chaotic neurons with memristor synapse is discussed, and synchronization mechanism is also found. Finally, we have also derived the sufficient conditions of chaotic synchronization in unidirectional coupled neuron circuits and bidirectional coupled neuron circuits respectively, which are that the parameter of memristor synapse must meet certain conditions. These results of theoretical analyses have been confirmed by numerical simulation.     

基于分数阶忆阻器的混沌电路分析与设计

提出了一种新型的分数阶忆阻混沌电路.首先,建立了分数阶忆阻器的数学模型,通过数值仿真验证了分数阶广义忆阻器满足忆阻器的基本特性.然后,将分数阶广义忆阻器与蔡氏振荡电路相结合,建立了一种基于分数阶广义忆阻器的混沌电路模型.通过稳定性理论,对分数阶系统的稳定性进行了分析.为了进一步研究电路参数对系统动态行为的影响,利用相位...     

A novel digital logic implementation approach on nanocrossbar arrays using memristor-based multiplexers

This paper presents and evaluates a novel multiplexer (MUX) composed of memristive devices and nanowire crossbar arrays. The switching behavior of memristors is employed to reveal the desired output state. By applying a sequence of appropriate voltage pulses to the developed MUX, the output is derived and can be transferred through read/write CMOS circuitry. The performance is verified with the SPICE simulator including a threshold-type memristor model. Using the proposed MUXes instead of memristor-based NAND gates, the routing effects that are a major challenge for implementing combinational logic in hybrid circuits can be reduced. Our evaluation results show that both density and delay are effectively improved in pure-MUX-based fabrics.     

Memristor-based genetic algorithm for image restoration

This paper explores a way of deploying the classical algorithm named genetic algorithm (GA) with the memristor. The memristor is a type of circuit device with both characteristics of storage and computing, which provides the similarity between electronic devices and biological components, such as neurons, and the structure of the memristor-based array is similar to that of chromosomes in genetics. Besides, it provides the similarity to the image gray-value matrix that can be applied to image restoration with GA. Thus, memristor-based GA is proposed and the experiment about image restoration using memristor-based GA is carried out in this paper. And parameters, such as the size of initial population and the number of iterations, are also set different values in the experiment, which demonstrates the feasibility of implementing GA with memristors.¹     

一种单输入控制器下的忆阻混沌同步电路设计与实现

该文提出一种在单输入控制器下基于忆阻器的混沌同步模拟电路设计及其实现方法,并将它应用于基于忆阻混沌同步的保密通信.首先,基于混沌同步理论,构建了混沌同步系统及保密通信模型,并设计实现了一种4阶压控忆阻混沌电路和混沌加密解密电路.其次,将所设计的忆阻混沌电路作为混沌驱动和响应电路,根据它们的误差系统设计了一种单输入混沌同...     

新型的平面双模椭圆函数带通滤波器

根据传统的方形贴片双模滤波器,提出了一种新颖的带有两个切角的平面双模带通滤波器结构.该结构使用单个贴片谐振器并且没有耦合缝隙,通带两端各有一个衰减极点,有效减小了滤波器的辐射损耗.对该滤波器结构进行改进,又提出了一种带有两个相互正交、长度不等槽线的双模椭圆函数带通滤波器结构.该滤波器在中心频率1.8GHz处,回波损耗达到31.53 dB,通带内最小插损达到0.01 dB,3 dB相对带宽为19.44%.采用Ansotf公司的En-sem ble 8.0仿真软件进行的仿真研究.仿真结果表明该结构可以更加有效地减小辐射损耗,增加带宽,且体积比传统滤波器减小了约40%,有利于小型化.     

低损耗双模微带贴片带通滤波器研究

首先提出了一种新颖、简单的带有两个切角的双模微带带通滤波器结构。该结构使用单个贴片谐振器并且没有耦合缝隙,通带两端各有一个衰减极点,可以有效减小滤波器的辐射损耗。对该滤波器结构进一步改进,又提出了一种中心频率1.8GHz相互正交槽线的新型双模微带带通滤波器结构。该滤波器在中心频率1.8GHz处,回波损耗达到31.65dB,通带内最小插损为0.01dB,3dB带宽为19.44%。研究结果表明该结构可以进一步减小辐射损耗,并且可以减小滤波器的体积,有利于小型化。     

A novel microstrip square-loop dual-mode bandpass filter with simultaneous size reduction and spurious response suppression

In this paper, a new capacitively stepped-impedance resonator(CSIR) is proposed to develop the microstrip square-loop dual-mode bandpass filter. Using this new design, simultaneous size reduction and spurious response suppression for the dual-mode bandpass filter can be achieved. An analytical formulation of this novel resonator is given in order to elucidate the spurious frequencies relocation design. Together with this formulation, a generalized dual-mode bandpass filter model is developed so as to ease the analysis of transmission zero and insertion loss. A prototype filter is designed at 900MHz with 1.5% fractional bandwidth. Significant spurious suppressions up to 33 and 35 dB are measured at 1.8 and at 2.7 GHz, respectively. A circuitry size reduction of 54% is achieved when compared with that of the conventional structure. Moreover, the CSIR allows frequency tuning and, thus, a varactor-tuned filter is designed and a measured tunable center frequency between 1.5-1.62GHz is demonstrated. Utilizing the proposed structure, not only size reduction,as well as spurious response suppression, but also center frequency tuning can be achieved.     

新型双模介质波导滤波器

为满足5G基站射频前端的要求,提出了一种新型双模介质波导滤波器.在表面镀银的介质填充波导腔里设置两个盲孔和一个耦合槽,可有效控制一对TE201奇偶模.应用上述结构,设计了一个单腔双模滤波器、一个三腔四阶滤波器和一个六腔七阶滤波器.仿真和测试结果表明,在同样阶数下,引入一个双模谐振器能够有效减小滤波器体积:二阶滤波器体积...     

一种基于DGS结构的新型双模双通带滤波器

提出了一种新颖的基于缺陷地结构(DGS)的双模双通带滤波器.该滤波器由印制板顶面的一个方形谐振单元和另一个巧妙嵌入在印制板底面DGS中的方形谐振单元并联构成,具有结构紧凑、易于加工的特点.每个谐振单元都具有双模单通带传输特性,可通过公共馈线同时激励实现双模双通带滤波.两个谐振单元的谐振频率相对可调,提高了设计上的灵活性.为减少辐射损耗并改善高频通带插损,使用准共面波导缺陷地结构对底面谐振单元进行了改进.最后,实验制作了两种双模双通带滤波器,测试结果与仿真结果吻合较好.     

Memristor-based combinational circuits: A design methodology for encoders/decoders

The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2ⁿ×n (n×2ⁿ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.     

Memristor based N-bits redundant binary adder

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results.     

新型微扰结构双模贴片带通滤波器设计

针对微带滤波器高性能小型化的需求,提出了一种方环形微扰单元的双模贴片带通滤波器的设计.该滤波器由方形贴片作为谐振器,输入、输出端口采用直接馈电,具有对称结构.利用在方形贴片上蚀刻出方环形缺口的方式,对方形贴片谐振器进行微扰,实现双模滤波器.通过电磁仿真软件Ansoft HFSS分析了微扰单元的特性,对双模滤波器的性能进...     

基于数字正交变换的双模DRFM技术研究

随着电子战技术的发展,对数字射频存储器（DRFM）的要求越来越高,传统的基于模拟正交变换的单一量化方式DRFM难以满足战场的需求.因此提出了基于数字正交变换方法的幅度、相位双模体制DRFM结构,并对Hilbert滤波法、低通滤波法和多相滤波法这3种正交变换方法的性能进行分析.该双模DRFM相比传统DRFM具有实现简单、功能丰富、适用范围广且镜像抑制比高等优点,特别适合于侦干一体化、小型化的发展趋势,仿真结果表明了双模DRFM的有效性.     

T形贴片双模微带带通滤波器

基于传统的T形贴片双模微带带通滤波器,提出了一种新型的加入缝隙耦合的T形双模微带带通滤波器。在T形贴片谐振器的两侧以缝隙耦合的方式插入馈线,并对其进行了优化。优化后的滤波器能在通带两侧都产生衰减极点,提高了阻带的抑制能力,对其进行了仿真。仿真结果表明,该滤波器通带的中心频率为5.0 GHz,与实测结果基本一致,滤波器尺寸为34 mm×24 mm,保证了滤波器的小型化。     

双模方形带通滤波器的分析、建模及设计

本文报道一种利用谐振器中缺口位置设计双模带通滤波器的新方法.用这种方法既可以实现具有一对传输零点的双模带通滤波器,也可以实现无传输零点的双模带通滤波器.通过分析缺口位置对谐振器内电场模式分布的影响,建立了双模滤波器的拓扑结构图.利用全波仿真软件,基于不同的缺口位置设计了中心频率为2.05GHz,带宽为100MHz的两种...     

微波线性相位双模介质滤波器

本文讨论了用双模介质加载谐振腔实现的微波线性相位滤波器结构，在非级联耦合的诸振腔之间引入一个交叉耦合，以改善通带内的时延平坦特性，给出了用模匹配法计算介质加载谐振腔的谐振频率和谐振腔之间耦合系数的方法。介绍了采用这种方法构成的滤波器的实际设计方法。最后制作了用这种方法设计出的滤波器，给出的实测结果表明它不仅可满足幅频特性的滤波要求，而且具有良好的通带时延特性。     

基于忆阻器的感存算一体技术综述

忆阻器的低功耗、高响应、纳米级、非易失性等特性,在实现非冯·诺依曼计算架构中展现出巨大潜力.基于忆阻器的高密度横梁阵列可实现数据存储及并行计算一体的逻辑电路和类脑计算电路.此外,纳米传感器与忆阻器进一步集成,采集的信号直接送往忆阻器阵列进行运算和存储,感知、存储与计算一体化的芯片技术成为新的研究热点.该文对基于忆阻器的...     

Millimeter-Wave Ultra-Wideband Bandpass Filter Employing Dual-Mode Ring Resonators Fed by Step-Impedance Coupled Lines

This paper presents a novel millimeter-wave ultra-wideband (UWB) bandpass filter (BPF) based on microstrip dual-mode rectangular ring resonators. In order to get strong coupling between the input/output line and the dual-mode ring resonators, a step-impedance parallel-coupled structure is adopted for the design of the filter. On the other hand, transmission zeros are produced by the dual-mode resonator. As a consequence, the filter has low insertion-loss in its passband, sharp attenuation in its lower and upper stopbands and very wide stopbands. As an example, a filter with two dual-mode ring resonators is designed and fabricated. The measured frequency property of the fabricated filter shows good agreement with the simulated response.