基于聚偏氟乙烯的触力传感器结构优化分析

以聚偏氟乙烯(PVDF)作为触力传感器的敏感元件,通过控制变量的方法探究了PVDF触力传感器的上下衬底材料的类型和厚度对传感器灵敏度的影响.通过对压电材料的压电方程的理论计算,得到触力输入与电压输出的关系.有限元分析结果表明,上下衬底材料的厚度和弹性模量对触力传感器的灵敏度影响较大.当采用0.025 mm的PDMS作为上下衬底材料时,触力传感器的灵敏度达到0.527 mV/N.     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

Seeded growth of AlN crystals on nonpolar seeds via physical vapor transport

Seeded growth of AlN single crystals was demonstrated in an induction-heated, high-temperature reactor via a physical vapor transport (PVT) process. AlN seeds were prepared from a self-seeded boule containing large single-crystalline grains. Seeded growth was interrupted several times in order to refill the AlN powder source, and a dedicated process scheme was used to ensure epitaxial growth on the seed surface, after prior exposure to air. The growth temperatures were in the range of 2200–2300°C, and the reactor pressure was in the range of 500–900 torr of UHP-grade nitrogen during each growth run. Under these growth conditions, a seed (10 mm diameter) expanded at an angle of 45°, and a larger single crystal up to 18 mm in diameter was obtained. The as-grown surface had three facets, of which facet (1120) was smooth and featureless while the other two, (4150) and (2570), showed serrated morphologies. The double-crystal x-ray rocking curve and glow discharge mass spectroscopy analysis confirmed that the grown crystal was of high crystalline quality with low impurity incorporation.     

Piezoelectric and electrical properties of PZT-PSN thin film ceramics for MEMS applications

Piezoelectric and electrical properties of PZT-PSN ceramics have been investigated as a function of WO₃ addition from 0 to 6.0 wt%. The dielectric and piezoelectric characteristics of PZT-PSN ceramics have been investigated at different calcination (800–900°C) and sintering (1100–1300°C) temperatures. The grain size increased in proportion to adding the amount of WO₃ and increasing the sintering temperatures. Anisotropic properties of electromechanical coupling coefficient and piezoelectric coefficient are proven to be dependent on processing temperatures and amount of addition. For the specimen with 0.6 wt% WO₃ addition, using a calcination temperature of 800°C and a sintering temperature of 1100°C, the mechanical quality factor and electromechanical coupling coefficient were 1560 and 0.48, respectively. Thin films were deposited in situ onto Pt/Ti/SiO₂/Si substrates by pulsed laser deposition using a Nd:YAG laser. The microstructure, dielectric, electrical, and piezoelectric properties of thin films with the compound ceramics have been systematically investigated for microtransformer and MEMS applications.     

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm². The obtained average reference current is 6 nA having a slope of 5.5pA/°C.     

Sub-1 V,pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18 µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7 mV, with a temperature coefficient as low as 3.2 ppm/°C for 0 to 125 °C range, while the power consumption is 545 pW under a 420 mV power supply at 27 °C. The power supply rejection ratio and output noise without any filtering capacitor at 100 Hz are −54.5 dB and 2.88 µV/Hz^1/2, respectively. The active area of the fabricated chip is 0.00332 mm².     

Response time and mechanism of Pd modified TiO2 gas sensor

In this work, gas response properties of Pd modified TiO₂ sensing films are discussed when exposed to H₂ and O₂. TiO₂ films are surface modified in PdCl₂-containing solution by the dipping method and treated for different treatment times to get different surface states. X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM) and Kröger–Vink defect theory are used to characterize the sensing films. The gas response properties indicate that the sensor response time which related to the rate of change of sensor resistance is affected by the activation energy (E). In particular, the sensor treated at 900 °C for 2 h exhibits a response time of about 20–240 ms when exposed to H₂ and 40–130 ms when exposed to O₂ at 500–800 °C.     

Nano-Engineered Carbon Fibre-Based Piezoelectric Smart Composites for Energy Harvesting and Self-Powered Sensing

The integration of piezoelectric materials onto carbon fiber (CF) can add energy harvesting and self-power sensing capabilities enabling great potential for “Internet of Things” (IoT) applications in motion tracking, environmental sensing, and personal portable electronics. Herein, a CF-based smart composite is developed by integrating piezoelectric poly(3,4-ethylenedioxythiophene) (PEDOT)/CuSCN-coated ZnO nanorods onto the CF surfaces with no detrimental effect on the mechanical properties of the composite, forming composites using two different polymer matrices: highly flexible polydimethylsiloxane (PDMS) and more rigid epoxy. The PDMS-coated piezoelectric smart composite can serve as an energy harvester and a self-powered sensor for detecting variations in impact acceleration with increasing output voltage from 1.4 to 7.6 V under impact acceleration from 0.1 to 0.4 m s⁻². Using epoxy as the matrix for a CF-reinforced plastic (CFRP) device with sensing and detection functions produces a voltage varying from 0.27 to 3.53 V when impacted at acceleration from 0.1 to 0.4 m s⁻², with a lower output compared to the PDMS-coated device attributed to the greater stiffness of the matrix. Finally, spatially sensitive detection is demonstrated by positioning two piezoelectric structures at different locations, which can identify the location as well as the level of the impacting force from the fabricated device.     

A remote pressure sensor with digital signal interface

A high performance pressure sensor circuit is described with a digital signal interface for accurate remote sensing of pressure. The signal conditioning circuitry converts sensor resistance variation into a digital signal. Automatic offset error correction prevents long term and temperature drift effects on overall performance. The digitized signal is detected remotely over two wires by means of optical or ferrite coupling. The same two wires were used for power supply delivery. Floating operation allows good performance in a noisy environment. Test results have shown less than 0-25 psi/°C input equivalent pressure error in a temperature range of – 25°C to +75°C. The non-linearity was less than 0-2% in a dynamic pressure range of 500/1 at room temperature.     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

A 2.87 ppm/°C 65 nm CMOS bandgap reference with nonlinearity compensation

Based on the review and analysis of two recently reported low temperature coefficient (TC) bandgap voltage references (BGRs), a new temperature compensation technique is presented. With the double-end piecewise nonlinearity correction method, the logarithm cancellation technique and the mixed-mode output topology, a BGR with high-temperature stability is realised based on 65?nm CMOS low-leakage process. The post-simulation results using Spectre show that this BGR produces an output voltage of about 953?mV with 2.5?V supply voltage, and the output voltage varies by only 0.16?mV from ?40°C to 125°C. This low TC BGR has been used in a 65?nm CMOS touch screen controller, and the measurement shows that the output voltage of this BGR is about 949?mV varying by 0.44?mV from ?40°C to 125°C. The TC of this BGR is about 2.87?ppm/°C, meeting the requirement of high-precision SoC application.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Failure and stress analysis of through-aluminum-nitride-via substrates during thermal reliability tests for high power LED applications

The objective of this study is to evaluate the reliability of through-aluminum-nitride-via (TAV) substrate by comparing those experimental results with the finite element simulation associated with measurements of aluminum nitride (AlN) strength and the thermal deformation of Cu/AlN bi-material plate. Two reliability tests for high-power LED (Light emitting diode) applications are used in this study: one is a thermal shock test from − 40 °C to 125 °C, the other is a pressure cook test. Also, the strength of AlN material is measured by using three-point bending test and point load test. The reliability results show that TAV substrates with thicker Cu films have delamination and cracks after the thermal shock test, but there are no failure being found after the pressure cook test. The determined strengths of AlN material are 350 MPa and 650 MPa from three-point bending test and point load test, respectively. The measurement of thermal deformation shows that the bi-material plate has residual-stress change after the solder reflow process, also indicating that a linear finite element model with the stress-free temperature at 80 °C can reasonably represent the stress state of the thermal shock test from − 40 °C to 125 °C without considering Cu nonlinear effect. The further results of the finite element simulation associated with strength data of AlN material have successfully described those of the reliability test.     

A high speed low jitter LVDS output driver for serial links

A high speed, low jitter low voltage differential signaling (LVDS) output driver for high speed serial transmission is presented. Based on the comparison among four typical output driver architectures and the analysis of the output signal swing, an additional differential termination is addressed at the source of the driver to improve the signal integrity (SI). The stipulated common mode voltage is achieved over process, voltage, temperature (PVT) variations without trimming methodology, by means of a common mode feedback (CMFB) circuit and a novel high order temperature compensation bandgap reference. The simulation results show the temperature coefficient (TC) of the bandgap is only 1.77 ppm/°C. The whole driver circuit is implemented in SMIC 0.18 μm CMOS technology. It provides an output differential mode voltage of 567 mV and a common mode voltage of 1.201 V at 2 Gbps, and consumes 15.41 mA total current with a 2.5 V power supply. The output root mean square (RMS) jitter of the driver is only 7.65 ps.     

Effects of high-temperature rapid thermal annealing for seed layers on the crystallographic evolution in hydrothermal ZnO nanostructures

In this work, we investigated effects of high temperature rapid thermal annealing for the zinc oxide (ZnO) seed layers on the growth morphology and crystal orientation of hydrothermal ZnO nanorods (NRs). The seed layers were prepared by sol–gel spin coating and annealed by two-step rapid thermal processes at different peak temperatures ranging from 600 to 900 °C for a short time period of 1 min. The seed layers annealed in a temperature range of 600–800 °C were all polycrystalline; however, they exhibited a highly Zn-deficient amorphous state when annealed at 900 °C as observed by X-ray photoelectron spectroscopy, X-ray diffraction (XRD), and cross-sectional transmission electron microscopy (TEM). The vertical NRs normal to the substrate were grown along [001] direction atop the polycrystalline seeds annealed at 600–800 °C, whereas different growth morphology of flower-like NRs was observed on the seeds annealed at 900 °C with the strongest XRD peak along the [100] orientation. From our cross-sectional TEM analysis, this flower-like architecture was initiated from the pioneer crystals laterally grown along [001] direction guiding the subsequent growth of petal NRs oriented by a slight difference in growth direction.     

MFC在水中摆动时输出开路电压幅值研究

利用柔性压电材料从流体的流动中获取能量已成为一个研究热点。该文研究了一种压电纤维复合材料(MFC)在水中摆动激励下的压电特性,建立了MFC压电纤维片在水中摆动激励下的数学模型,并结合MFC压电纤维片的压电输出机理得出影响MFC压电纤维片输出开路电压幅值大小的因素。最后设计搭建了MFC压电纤维片在水中摆动的试验台,利用该试验台验证了模型的正确性,并研究了MFC压电纤维片在不同摆动频率下的压电特性。结果表明,在摆角幅值为10°,摆动频率为1.75 Hz时,MFC的输出开路电压幅值取得最大值(600 mV),继续增大摆动频率,输出开路电压幅值逐渐减小。     

Flexible Battery-Free Wireless Sensor Array Based on Functional Gradient-Structured Wood for Pressure and Temperature Monitoring

Approximately 4.5% to 7.0% of hospitalized patients suffer from pressure ulcers. Mitigating risks for pressure ulcers through sensors remains a challenge and a high requirement. A simple, low-cost, battery-free, multi-parameter passive wireless flexible sensor (MPWFS) for all-around pressure and temperature monitoring to prevent pressure ulcers is developed. The pressure sensing unit is fabricated with functional gradient-structured balsa wood and has high sensitivity of 0.34 kPa⁻¹ with a wide detection range of 0–20 kPa. The temperature sensing unit, which is 0.4 mm × 0.2 mm, is embedded in the surface of the pressure sensing unit, enabling temperature monitoring with a resolution of 0.1 °C. The flexible Radio Frequency energy-harvesting unit, data acquisition, and processing, as well as Bluetooth-Low-Energy wireless transmission, are integrated within a 20 mm × 20 mm unit. It acquires continuous temperature and pressure data without a battery at any position more than 1 m away from the power transmitter. Moreover, the combination of the sensor array design with a mobile terminal provides the MPWFS's various benefits, including tracking changes in the supine posture, warning about pressure ulcers, and monitoring falls out of bed. This study presents a new method for long-term bedridden patient care.     

Effect of annealing on photoluminescence of passivated porous silicon

Photoluminescence (PL) of annealed porous silicon (PS) without and with nitrogen passivation has been investigated. The un-nitridated PS emits intense blue and green light, while that with passivation, emits only blue light and its intensity increases obviously. It is found that the PL intensity of the nitrified PS decreases with increasing temperature from 300 °C to 700 °C, but increases drastically after annealing at 800 °C and 900 °C, which might be due to the formation of Si–N bonds that passivates the non-radiative centers (Si dangling bonds) on the surface of PS samples. However, the intensity of the un-nitridated PS decreases continuously with increasing temperature from 300 °C to 900 °C, which might be due to desorption of hydrogen.     

A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

The paper presents a novel high-order temperature-compensated subthreshold voltage reference that utilizes temperature characteristics of the gate-to-source voltage of subthreshold MOS transistor. The proposed high-order temperature-compensated voltage reference has been designed using two CMOS voltage references and a current subtraction circuit to achieve a low temperature coefficient over a wide temperature range. The proposed circuit offers an output reference voltage of 250.8 mV, line sensitivity of 0.0674%/V and temperature coefficient of 37.4 ppm/°C for the temperature range varying from???20 \(\mathrm{^\circ{\rm C} }\) to 140 °C at nominal conditions. The power supply rejection ratio is obtained as???46.02 dB at a frequency of 100 Hz and???41.91 dB at a frequency of 1 MHz. The proposed circuit shows an output noise of 1.86 \(\mathrm{\mu V}/\surd \mathrm{Hz}\) at 100 Hz and 259.72 \(\mathrm{nV}/\surd \mathrm{Hz}\) at 1 MHz. The proposed circuit has been designed in BSIM3V3 180 nm CMOS technology using Cadence tool. The corner analysis of the proposed circuit has also been performed to show its performance in extreme conditions. The proposed circuit occupies a small chip area of 51 \(\upmu\)m?×?75.3 \(\upmu\)m.