一种稳定的RLC互连Π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型，并讨论了它在互连树延时和逻辑门延时估计中的应用．结果表明，该模型与已有方法相比精度有一定程度的提高．     

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

互连封装结构电特性分析中的改进PEEC三维建模

本文提出了一种改进的PEEC模型,为便于在大规模互连封装结构分析中利用规模缩减技术,它以描述系统的状态方程代替了具体的等效电路.为此它以矢量磁位的积分表达式和洛仑兹规范代替了矢量磁位和标量电位的积分表达式,对积分方程进行展开.这样做可以避免复杂介质结构中的电容矩阵提取,大大节省了计算时间.这一模型可方便地嵌入更大的系统进行分层次的综合分析和利用PVL等规模缩减技术.数值计算的结果与其他文献吻合较好,表明该方法有较高的可靠性.     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.     

静态时序分析及其在IC设计中的应用

讨论了静态时序分析算法及其在IC设计中的应用。首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。最后通过一个完整的IC设计流程介绍了静态时序分析的应用。     

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.     

软件测试中设计技法与测试过程的研究

软件测试是一门重要的、具有广泛应用的学科,随着应用系统的不同,软件的测试方法呈现多样性。作者在软件开发过程中,曾经进行过大量的软件测试工作,编写大量的测试项,根据以往的工作经验,总结了软件测试中的主要问题。在此基础上,对已有的测试方法和系统进行分析,详细讨论了测试项设计方法,并对今后的发展方向进行展望。     

动态时序分析及其在纳米级IC设计中的应用

文章讨论了动态时序分析算法及其在纳米级IC设计中的应用.首先,针对静态敏化算法存在的静态伪路径(Static False Path)问题,提出了动态敏化算法,分析了静态敏化和动态敏化的关系.最后讨论了在电源噪声和串扰噪声影响下的动态时序分析.实验结果表明,串扰噪声条件下的动态时序分析结果比静态时序分析给出的保守结果准确得多.     

后驱动技术在电子测试维修中的应用

讨论电子器件的故障形式,分析传统测试方法在现代电子测试中的问题,重点分析在线电子测试中器件隔离问题,详细研究后驱动技术及其应用,并在此基础上,分析采用后驱动技术对电子器件的安全容限。最后,对在线测试仪的应用和发展进行了展望。     

雷达软件测试管理平台的研究及应用

文中针对当前雷达产品软件测试现状,详细介绍了测试管理工具QC（Quality Center）在雷达软件测试模型、测试需求管理、测试设计执行和缺陷管理等主要软件测试管理方面的应用解决方案。该方案实现了雷达软件测试中各种测试资源的有效整合,可以大大提高雷达软件测试效率和测试质量,取得较好的测试项目管理效果。最后,结合雷达产品,给出雷达软件测试管理平台在雷达产品软件测试中的具体应用。     

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure

ADCs are fully characterized by both static and dynamic parameters. Testing methods usually combine a histogram-based approach with a spectral analysis to determine the complete set of ADCs parameters. In the view of a unique test procedure, this paper investigates the correlation between both kinds of parameters. Experimental results demonstrate that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset, gain and non-linearity errors, opening the way of a low-cost test strategy in the frequency domain.     

一种新的广义阻抗变换器模型及应用

本文在微波网络综合理论中，提出一种新的广义阻抗变换器模型，它是Ｋ，Ｊ变换器的最一般推广，可应用于带任意复杂不连续性的微波滤波器，阻抗变换器和耦合器的设计，并能解决对称和反对称网络两种情况，文中给出了设计实例。     

基于抽象解释的变量值范围分析及应用

精确的变量值范围分析对于编译器优化、静态分析和软件测试至关重要.在介绍抽象解释理论的基础上,扩展了经典的区间抽象,首次提出区间集的概念并定义了新的数值型区间集代数、布尔型和引用型区间代数,给出了统一的基于抽象解释的变量值范围分析方法RABAI,引入拓宽算子计算循环体变量范围,对过程参数定义了特殊的未定义取值(undef...     

一种基于循环前缀的OFDM时频同步新算法

OFDM符号是由多个子载波信号叠加而成,为确保各子载波之间的正交性,就对载波间的同步有很严格的要求,否则将造成信道间干扰和符号间干扰,严重影响OFDM系统的性能。提出一种新的基于循环前缀的OFDM时频同步算法,通过仿真,将新算法和传统的ML算法及集相关算法相比较。仿真结果表明,新算法具有更好的频偏和定时估计性能。     

正交复用QAM系统的定时和载波相位跟踪新算法

在数字信号传输系统中，正交复用ＱＡＭ（ＯＭＱＡＭ）是目前最有效的一种抗信道失真传输技术，但它对系统的定时偏移和载波相位误差非常敏感。本文基于高阶累积量技术，导出了一种新的ＯＭＱＡＭ系统定时和载波相位的跟踪算法。计算机仿真证实了这一理论分析结果，并同原有的Ｈｉｒｏｓａｋｉ算法做了比较     

5G毫米波基站的OTA 校准与测试方法研究

5G毫米波基站采用大规模多输入多输出(Massive MIMO)阵列的形式,且空口(Over the Air, OTA)测试将成为首选的5G 毫米波基站测试方案。文中针对数字波束成形形式的5G 毫米波基站大规模MIMO 阵列,给出了相应的OTA 校准与测试解决方案,提出了波束等效全向辐射功率(Beam Equivalent Isotropic Radiated Power,BEIRP)的概念,并将传统的射频传导测试指标进行了波束域的拓展,即定义了波束误差矢量幅度(Beam Error Vector Magnitude,BEVM)和波束邻道功率抑制比(Beam Adjacent Channel Leakage Ratio,BACLR)的指标。通过仿真与实验, 验证了相关方法、指标的可操作性与合理性,以期对5G 毫米波测试规范的制订有参考价值。     

Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.     

基于Cadence—Allegro的高速PCB设计信号完整性分析与仿真

信号完整性问题已成为当今高速PCB设计的一大挑战,传统的设计方法无法实现较高的一次设计成功率,急需基于EDA软件进行SI仿真辅助设计的方法以解决此问题。在此主要研究了常见反射、串扰、时序等信号完整性问题的基础理论及解决方法,并基于IBIS模型,采用Cadence．Alkgro软件的Specctraquest和Sigxp组件工具时设计的高速14位ADC／DAC应用景婉实制进行了SI仿真与分析,验证了常见SI问题解决方法的正确性。     

TMN信息模型一致性测试中并行测试调度方法的研究

讨论了ＴＭＮ信息模型一致性测试中并行测试调度的设计方法。采用基于有限自动机的设计方式来设计并行测试调度功能实体，解决了测试过程中的并行测试问题，该方法可以缩短测试时间，提高测试效率。