不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2.1nm,栅长为0.135μm的pMOSFET中HALO掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HALO掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HALO掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology

The negative threshold voltage (V/sub t/) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V/sub t/ shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V/sub t/ shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V/sub t/ drift is proposed.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 /spl mu/m/sup 2/ is fabricated based on 0.13-/spl mu/m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V/sub t/ in erase while programming is done by lowering a local V/sub t/ through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.     

High-field effects in silicon nitride passivated GaN MODFETs

This paper presents a detailed study of high-field effects in GaN MODFETs. Degradation of DC characteristics and change of flicker noise due to hot electron and high-reverse current stresses in Si/sub 3/N/sub 4/ passivated GaN MODFETs have been investigated. The authors observe that during hot electron stress, electron trapping in the barrier layer and interface state creation occur. These cause a positive shift of V/sub t/, reduce I/sub D/, skew the transfer characteristics, and degrade g/sub m/. Flicker noise (1/f) measurements show that after hot electron stress, the scaled drain current noise spectrum (S/sub I(D)//I/sub D//sup 2/) decreases in depletion, but increases only slightly in strong accumulation, corroborating the creation of interface states but only a small creation of transition-layer tunnel traps that contribute to 1/f noise. During high-reverse current stress, electron trapping dominates for the first 50-60 s and then hole trapping and trap creation begin to manifest. However, there still is net electron trapping under the gate after one hour of stress. The degradation processes bring about a positive shift of V/sub t/, degrade I/sub D/ and g/sub m/, and increase reverse leakage. After high-reverse current stress, S/sub I(D)//I/sub D//sup 2/ increases substantially in strong accumulation, indicating the creation of transition layer tunnel traps.     

Real impact of dynamic operation stress during burn-in on DRAM retention time

The burn-in (BI) mechanism in connection with the dynamic operation stress (DOS) has been investigated to examine the real impact on dynamic random access memory (DRAM) reliablity. In this paper, the wafer burn-in (WBI) method with equivalent screening efficiency as the package burn-in (PBI) is implemented by employing DOS. It is found that retention time degradation by BI stress in DRAM with potentially lethal defects is mainly attributed to DOS-induced hot carrier (HC) degradation of DRAM cell. Hot electrons injection in Si-SiO/sub 2/ interface brings about lots of interfacial states as well as the electrical field modification at the gate-overlapped region, causing the degradation of retention time. This is clarified by an anomalous threshold voltage (V/sub T/) shift, and an increase of gate-induced drain leakage (GIDL) after dc HC stress having the identical stress voltage as DOS. Moreover, it is proved that a WBI procedure with the relevant DOS can screen out weak bits effectively, compared to that with only static stress.     

A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n/sup +/ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V/sub t/) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state V/sub t/ distribution, which will reduce overerasure significantly.     

Threshold voltage of submicron Ga/sub 0.47/In/sub 0.53/As HIGFETs

Presents threshold voltage data for Al/sub 0.48/In/sub 0.52/As/Ga/sub 0.47/In/sub 0.53/As/InP heterostructure insulated gate FETs (HIGFETs) with gate lengths from 1.2 mu m to 0.4 mu m. The refractory-gate, self-aligned fabrication process was applied to MBE-grown structures with 300 AA Ga/sub 0.47/In/sub 0.53/As channels and semi-insulating superlattice buffers to achieve sharp pinchoff with excellent threshold uniformity. HIGFETs with L/sub g/=1.2 mu m showed a threshold voltage of -0.076+or-0.019 V, making them well-suited to application in direct-coupled FET logic (DCFL) circuits.<>     

A new asymmetrical halo source GOLD drain (HS-GOLD) deepsub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 μm. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

HALO结构pMOSFETs在V_g=V_d/2应力模式下应力相关的热载流子退化

研究了超薄栅(2 .5 nm )短沟HAL O- p MOSFETs在Vg=Vd/ 2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证     

Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature V/sub t/ drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature V/sub t/ drift is significantly decreased by using bottom oxide (BOX) with the thickness T/sub BOX/<50 /spl Aring/. Excellent retention properties are preserved for T/sub BOX/ up to 33 /spl Aring/. The results of single-cell studies were confirmed on 2 Mb memory arrays that underwent up to 1000 program/erase cycles. Peculiarities of hole injection into the nitride of oxide-nitride-oxide in the erase operation are considered for explanation of the observed results. The improvement is associated with a lesser amount of holes used in the erase.     

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.     

The effect of IrO/sub 2/--IrO/sub 2/--Hf--LaAlO/sub 3/ gate dielectric on the bias-temperature instability of 3-D GOI CMOSFETs

We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-/spl kappa//Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 /spl mu/m CMOSFETs. The devices used IrO/sub 2/--IrO/sub 2/-Hf dual gates and a high-/spl kappa/ LaAlO/sub 3/ gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-/spl kappa//GOI p-and n-MOSFETs displayed threshold voltage (V/sub t/) shifts of 30 and 21 mV after 10 MV/cm, 85/spl deg/C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-/spl kappa/-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.     

Effects of deuterium anneal on MOSFETs with HfO/sub 2/ gate dielectrics

The effects of high-temperature (600/spl deg/C) anneal in a dilute deuterium (N/sub 2/ : D/sub 2/= 96 : 4) atmosphere was first investigated and evaluated in comparison to high-temperature forming gas (N/sub 2/ : H/sub 2/= 96 : 4) anneal (600/spl deg/C) and nonanneal samples. The high-temperature deuterium anneal was as effective as the forming gas anneal in improving MOSCAP and MOSFET characteristics such as the C-V curve, drain current, subthreshold swing, and carrier mobility. These can be attributed to the improved interface quality by D/sub 2/ atoms. However, unlike the forming gas anneal, the deuterium anneal provided the hafnium oxide (HfO/sub 2/) gate dielectric MOSFET with better reliability characteristics such as threshold voltage (V/sub T/) stability under high voltage stress.     

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.     

An analysis of base bias current effect on SiGe HBTs

The anomalous dip in scattering parameter S/sub 11/ of SiGe heterojunction bipolar transistors (HBTs) is explained quantitatively for the first time. Our results show that for SiGe HBTs, the input impedance can be represented by a "shifted" series RC circuit at low frequencies and a "shifted" parallel RC circuit at high frequencies very accurately. The appearance of the anomalous dip of S/sub 11/ in a Smith chart is caused by this inherent ambivalent characteristic of the input impedance. In addition, it is found that under constant collector-emitter voltage (V/sub CE/), an increase of base current (which corresponds to a decrease of base-emitter resistance (r/sub /spl pi//) and an increase of transconductance (g/sub m/)) enhances the anomalous dip, which can be explained by our proposed theory.