共查询到20条相似文献,搜索用时 31 毫秒
1.
《Solid-State Circuits, IEEE Journal of》2009,44(1):195-207
A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications. 相似文献
2.
Jin-Ki Kim Sakui K. Sung-Soo Lee Itoh Y. Suk-Chon Kwon Kanazawa K. Ki-Jun Lee Nakamura H. Kang-Young Kim Himeno T. Jang-Rae Kim Kanda K. Tae-Sung Jung Oshima Y. Kang-Deog Suh Hashimoto K. Sung-Tae Ahn Miyamoto J. 《Solid-State Circuits, IEEE Journal of》1997,32(5):670-680
Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm2 and an effective cell size of 1.1 μm2 相似文献
3.
Design of a sense circuit for low-voltage flash memories 总被引:1,自引:0,他引:1
Tanzawa T. Takano Y. Taura T. Atsumi S. 《Solid-State Circuits, IEEE Journal of》2000,35(10):1415-1421
A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-μm flash memory process and successfully operated at a low voltage of 1.5 V 相似文献
4.
To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture 相似文献
5.
Nobukata H. Takagi S. Hiraga K. Ohgishi T. Miyashita M. Kamimura K. Hiramatsu S. Sakai K. Ishida T. Arakawa H. Itoh M. Naiki I. Noda M. 《Solid-State Circuits, IEEE Journal of》2000,35(5):682-690
We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-μm CMOS process, resulting in a 104.2-mm2 die size and a 1.05-μm2 effective cell size 相似文献
6.
In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-Vth select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized 相似文献
7.
Tae-Sung Jung Young-Joon Choi Kang-Deog Suh Byung-Hoon Suh Jin-Ki Kim Young-Ho Lim Yong-Nam Koh Jong-Wook Park Ki-Jong Lee Jung-Hoon Park Kee-Tae Park Jhang-Rae Kim Jeong-Hyong Yi Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1996,31(11):1575-1583
For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm2 die size and a 1.1 μm2 effective cell size 相似文献
8.
Taehee Cho Yeong-Taek Lee Eun-Cheol Kim Jin-Wook Lee Sunmi Choi Seungjae Lee Dong-Hwan Kim Wook-Ghee Han Young-Ho Lim Jae-Duk Lee Jung-Dal Choi Kang-Deog Suh 《Solid-State Circuits, IEEE Journal of》2001,36(11):1700-1706
A 116.7-mm2 NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-μm CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes, respectively. The two-step bitline setup scheme suppresses the peak current below 60 mA. The wordline ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage Vth distributions. With the small wordline and bitline pitches of 0.3-μm and 0.36-μm, respectively, the cell Vth shift due to the floating gate coupling is about 0.2 V. The read margins between adjacent two program states are optimized resulting in the nonuniform cell Vth distribution for MLC mode 相似文献
9.
To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme 相似文献
10.
《Solid-State Circuits, IEEE Journal of》2009,44(4):1227-1234
11.
Kang-Deog Suh Byung-Hoon Suh Young-Ho Lim Jin-Ki Kim Young-Joon Choi Yong-Nam Koh Sung-Soo Lee Suk-Chon Kwon Byung-Soon Choi Jin-Sun Yum Jung-Hyuk Choi Jang-Rae Kim Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1995,30(11):1149-1156
While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm2 die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA 相似文献
12.
《Solid-State Circuits, IEEE Journal of》2009,44(1):208-216
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and the design techniques, a memory cell size of 0.0021 mum2/bit per unit feature area which is smallest cell size and 2.5 MB/s program throughput with 2 kB page size which is almost equivalent performance compared to conventional planar device are realized. 相似文献
13.
Atsumi S. Umezawa A. Tanzawa T. Taura T. Shiga H. Takano Y. Miyaba T. Matsui M. Watanabe H. Isobe K. Kitamura S. Yamada S. Saito M. Mori S. Watanabe T. 《Solid-State Circuits, IEEE Journal of》2000,35(11):1648-1654
A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-μm triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 μm2 , the smallest yet reported for 0.25-μm CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized 相似文献
14.
Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-Vth nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words×16-bits SRAM test chip, fabricated with a 0.35-μm MTCMOS/SIMOX process (shortened effective channel length of 0.17 μm is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-μW and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads 相似文献
15.
Imamiya K. Sugiura Y. Nakamura H. Himeno T. Takeuchi K. Ikehashi T. Kanda K. Hosono K. Shirota R. Aritome S. Shimizu K. Hatakeyama K. Sakui K. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1536-1543
A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm2, which realizes a 130-mm2 , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput 相似文献
16.
Miyawaki Y. Ishizaki O. Okihara Y. Inaba T. Niita F. Mihara M. Hayasaka T. Kobayashi K. Omae T. Kimura H. Shimizu S. Makimoto H. Kawajiri Y. Wada M. Sonoyama H. Etoh J. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1551-1556
A 29-mm2, 16-Mb divided bitline NOR (DINOR) flash memory is fabricated using 0.25-μm triple-well three-layer-metal CMOS technology. Read access time is 72 ns at 1.8 V. A poly diode charge-pump technique improves pump efficiency and eliminates the body effect problem 相似文献
17.
Tae-Sung Jung Do-Chan Choi Sung-Hee Cho Myong-Jae Kim Seung-Keun Lee Byung-Soon Choi Jin-Sun Yum San-Hong Kim Dong-Gi Lee Jong-Chang Son Myung-Sik Yong Heung-Kwun Oh Sung-Bu Jun Woung-Moo Lee Haq E. Kang-Deog Suh Ali S.B. Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1997,32(11):1748-1757
A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm2, and the effective cell size including the overhead of string select transistors is 2.0 μm2 相似文献
18.
Takeuchi K. Satoh S. Tanaka T. Imamiya K. Sakui K. 《Solid-State Circuits, IEEE Journal of》1999,34(5):675-684
A new, negative Vth cell architecture is proposed where both the erased and the programmed state have negative Vth. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 μm, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a Vcc-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the Vth fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the Vth distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized 相似文献
19.
Kinoshita S. Morie T. Nagata M. Iwata A. 《Solid-State Circuits, IEEE Journal of》2001,36(8):1286-1290
This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory 相似文献
20.
Ohkawa M. Sugawara H. Sudo N. Tsukiji M. Nakagawa K. Kawata M. Oyama K.-i. Takeshima T. Ohya S. 《Solid-State Circuits, IEEE Journal of》1996,31(11):1584-1589
In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm2 die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed 相似文献