A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

一种高集成度TDD模式射频收发模块

文章介绍了一种高集成度TDD模式的射频收发模块,在移动通信的F频段(2015~2025 MHz),实现射频与数字基带互相转换,Tx功率达到2 W,接收NF小于2.1dB,收发EVM指标全面达到要求。     

基于单片机的GSM短信收发模块设计

本设计研究如何通过单片机的控制,实现GSM模块接收和发送简单数字、字母的短信。随着科技的发展,GPS和GSM的联合定位装置将给人们带来更大地方便,如何控制GSM模块将接收到的定位数据发送和回收,对后续的数据处理有至关重要的作用。本文使用MSP430单片机通过RS232串口与GsM模块通信,使用标准的AT命令来控制GsM模块实现各种无线通信功能。实验结果表明：该模块能够稳定的将定位数据以短信的方式进行传输。     

An integrated RF transceiver for DECT application

An integrated circuit (IC) is presented which implements the complete RF front-end solution for a digital enhanced cordless communications (DECT) cordless phone provided that a single-transistor LNA and a power amplifier are included on the application board. Focus has been put in the paper on the image rejection mixer which achieves image rejection mean values of 43 dB and on the fully integrated voltage-controlled oscillators which guarantees -134 dBc phase noise at 6.5-MHz offset over temperature and process variation. The circuit was fabricated in a high-performance low-cost 20-GHz silicon bipolar technology and assembled on a TQFP64 package. It was tested on the complete application board including the LNA and the power amplifier, and it fully complies with the ETSI TBR06 standard requirements. The internal power supply is 2.8 V     

GSM基站收发信机中的功率放大电路分析

基于爱立信公司的GSM基站收发信机原理,从电路方面对射频放大器进行了匹配分析和稳定性分析,说明了爱立信公司的GSM基站的一些特点.     

一种全CMOS工艺吉比特以太网串并-并串转换电路

本文介绍了一种单片集成的吉比特以太网串并－并串转换电路。在芯片中，模拟锁相环产生1．25GHz高速时钟（当芯片用于光纤网络，时钟速率就为1．06GHz)，同时一个10到1多路选择器完成并行数据到串行的转换。在接收端，差分输入信号依次经过均衡电路、双端－单端转换电路转换成数字信号。同时，数据和时钟提取电路提取出时钟，并将数据重新同步。最后，串并转换电路完成串行－并行转换和字节同步。实验芯片采用0．35μmSPTM CMOS工艺，芯片面积为1．92mm^2，在最高输入输出数据波特率条件下的功耗为900mW。     

Development of a photonic integrated transceiver chip for WDMtransmission

With the observed expansion of fiber-optic networks and the movement of line terminals towards the individual customer the need for cost-effective fabrication of customer access modules for interactive services arises. Monolithic integration of the module functions on InP is frequently seen as a means to reduce module costs. Here we describe a generic fabrication process for InP photonic integrated circuits and demonstrate an initial transceiver chip with transmit, receive and 1300/1530 nm wavelength division multiplexing functions. The chip output power reaches 1 mW at 1530 nm with a laser threshold current of 20 mA. The detection efficiency at 1300 nm is 0.1 A/W of fiber power     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.     

A 1.9-GHz single chip IF transceiver for digital cordless phones

A 1.9 GHz IF transceiver for the Japanese standard personal handy-phone system (PHS) is fabricated in a 0.8-μm BiCMOS process with 20 GHz npn. A down-mixer, up-mixer, variable attenuator, quadrature modulator, first and second PLL, and second VCO are included in the 3.4×3.0 mm² chip. The chip draws 24 mA in receive mode and 44 mA in transmit mode, operating from 3.0 V. A total vector error of 4% for the π/4 QPSK PN9 pattern includes the up-mixer and the dual PLLs     

An integrated circuit for GSM mobile communications

An integrated circuit for the Pan European GSM mobile communications system is described which performs GMSK digital modulation and front-end functions for both base and mobile stations. The circuit includes, as main functional blocks, a 10-bit D/A converter, a 13-MHz switched-capacitor interpolating filter, and a power buffer. A fully differential approach was used. The circuit has been fabricated using a 2-m CMOS process. The chip size is 6.7×5.3 mm². The overall circuit performance fully meets GSM specifications.     

System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip

Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques could be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.     

433/868/915MHz收发芯片nRF903

特点 nRF903是NORDIC公司最新推出的单片无线收发一体的芯片,采用了Bluetooth核心技术设计,在一个32脚的芯片中包括了三段高频发射、高频接收、PLL合成、I/Q调制、I/Q解调、多频道切换、异步通信接口等,是目前集成度最高的无线数据传输产品之一.     

全集成微电子神经桥芯片研究

Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is 4-2.5 V, and the chip area is 1.21×1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.     

倒装芯片组装集成电路开封方法

倒装芯片组装集成电路的结构与常规封装不同,导致现行开封技术不完全适用于倒装芯片组装集成电路。对不同封装形式的倒装芯片组装集成电路结构分析,找出目前制约开封技术的关键因素。以陶瓷及塑封封装倒装芯片组装集成电路为例,运用热风枪、高温预处理、机械应力及化学腐蚀等方法,提出了一套适用性强、效率高的综合性倒装芯片组装集成电路开封工艺技术,并通过实例进行验证和总结。通过运用该技术可以有效解决倒装芯片组装集成电路的开封问题,为后续标准的修订及破坏性物理分析提供依据和帮助。     

A transceiver circuit for ATM networks

This paper presents a transceiver digital circuit. The circuit is responsible for the emission of packets to the asynchronous transfer mode (ATM) network as well as for the manipulation of received ATM packets belonging to virtual connections. It has been designed to support data communication services. The circuit, which can be used in terminals or in interworking units and switches, implements basic functions of the lower layers of the ATM protocol reference model. The transmission functionality includes cell buffering, header error control, cell assembling, rate coupling and information insertion. The receiver realizes information extraction, rate decoupling, cell buffering, header error detection and correction, connection identity fields extraction and identification, cell disassembling and classification, and idle cell discarding functions. The circuit has been implemented on applications specific integrated circuit (ASIC) chips.     

一种应用于双载波正交频分复用的超宽带单片射频收发机

本文给出了一种用于双载波正交频分复用的超宽带单片射频收发机芯片。该芯片采用直接变频结构,片内共集成了两路接收机,两路发射机,一个双载波频率综合器并提供控制收发机工作状态的三线串行接口。此芯片使用台积电 0.13 微米射频CMOS工艺制造,尺寸为 4.5mmx3.6mm。测试结果表明：该收发机的接收机链路噪声系数为 5~6.2dB,最大增益为 78~84dB,可变增益为 64dB,带内和带外三阶交调点分别为-6dBm和 4dBm,在所有频带上都获得良好的输入匹配（S11<-10）;该收发机的发射机最大可输出-5dBm 功率,带内主要杂散均小于 -33dBc（镜像抑制<-33dBc,载波泄露<-34dBc）,典型的输出三阶交调点为 6dBm;该收发机的双载波频率综合器可以同时输出两路频率可独立配置的载波信号,其跳频时间小于1.2ns。在1.2V单电源供电下,整个射频芯片消耗最大电流为420mA。