A Chip for Linearization of RF Power Amplifiers using Predistortion based on a Bit-Parallel Complex Multiplier

This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.     

Resonant-Clock Latch-Based Design

This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their clock distribution networks. It also highlights RCL, a novel resonant-clock latch-based methodology that was used to design the two test-chips. RF1 and RF2 are 8-bit 14-tap finite-impulse response (FIR) filters with identical architectures. Designed using a fully automated ASIC design flow, they have been fabricated in a commercial 0.13 mum bulk silicon process. RF1 operates at clock frequencies in the 0.8-1.2 GHz range and uses a single-phase clocking scheme with a driven clock generator. Resonating its 42 pF clock load at 1.03 GHz with V_dd = 1.13 V, RF1 dissipates 132 mW, achieving a clock power reduction of 76% over conventional switching. RF2 achieves higher clock power efficiency than RF1 by relying on a two-phase clocking scheme with a distributed self-resonant clock generator. Resonating 38 pF of clock load per phase at 1.01 GHz with V_dd = 1.08 V, RF2 dissipates 124 mW and achieves 84% reduction in clock power over conventional switching. At 133 nW/MHz/Tap/InBit/CoeffBit, RF2 features the lowest figure of merit for FIR filters published to date.     

Over GHz low-power RF clock distribution for a multiprocessordigital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers^Lt; RO3003 high-frequency organic substrate     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter

Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs.     

Dynamic CMOS amplifiers

The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.     

CMOS on-chip clock for digital signal processors

An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.<>     

A 4-GHz clock system for a high-performance system-on-a-chip design

A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-μm single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48×1.00 mm²     

用于钙离子光频标的高性能脉冲时序产生方法

在钙离子光频标实验研究中,为了保证钟跃迁谱线的测量精度和光频标的锁定精度,方便自动控制实验进程,研究了基于LabVIEW的数字波形法结合数据采集卡产生多通道脉冲信号的方法。该方法采用多路数字信号序列同步输出的方法,由板卡的板载硬件时钟源作为定时器,通过编程从计数器/定时器输出频率连续的矩形脉冲输入到采集卡作为控制各路数字波形输出的同步时钟,数字信号输出过程的数字通道样本输出率可达0.4MHz,脉冲宽度的精度可稳定达到2.5µs,上升延迟小于50ns,而且多路脉冲都以同一个计时起点开始,因此具有很好的分辨率、同步性和稳定性。     

A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-μm DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz     

High-speed CMOS circuit technique

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz     

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

A design is presented for an 8-bit/spl times/8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-/spl mu/m CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated.     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

一种新颖的低非线性全数字多相时钟产生电路

通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220?MHz, a jitter with 4?ps resolution can be injected.     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

Slot Synchronization in Optical PPM Communications

Maintaining slot clock synchronization in a baseband pulse position modulated (PPM) communication link is vital to its performance. This paper examines the slot clocking design associated with a direct detection, photodetecting optical PPM system. Although theoretical PPM synchronizers for optical links have been derived in the past, there is still interest in finding more practical, simpler, and easier-to-implement clocking subsystems. In this paper several types of practical slot synchronizers are considered. A basic design involving analog correlators and slot gating is presented, along with an indication of its performance. Several alternative designs are also presented, including digital synchronizers in which time samples are used for loop control. The advantage in digital systems is that more extensive processing can be handled in software, allowing the loop to perform closer to the ideal. Design procedures for digital clocking are presented, and optimal laser pulse shaping and filtering are discussed. Performance in terms of loop models and tracking error variance is included.