杂质不完全离化对SiC MOSFET的影响

在分析SiC中杂质部分离化时,考虑了Frenkel-Pool效应,通过求解SiC MOS表面空间电荷区中的一维Poisson方程,提出了一个新的SiC MOSFET反型层薄层电荷(charge-sheet)数值模型.对SiC中杂质不完全离化的研究表明,杂质原子较大的离化能、高的掺杂浓度以及低温会使不完全离化的影响增强,对于SiC MOSFET,杂质不完全离化的影响主要在亚阈区.     

基于表面势的N沟4H-SiC MOSFET I-V特性解析模型

报道了一种适于模拟 n沟 4H-Si C MOSFET直流 I-V特性的整体模型。该模型充分考虑了常温下 Si C中杂质不完全离化以及界面态电荷在禁带中不均匀分布的影响 ,通过解析求解泊松方程以及牛顿 -拉夫森迭代计算表面势 ,得到了表面电场以及表面势的分布 ,并以此为基础采用薄层电荷近似 ,计入栅压引起的载流子迁移率退化效应 ,导出了可用于所有器件工作区的统一漏电流解析表达式。当漏偏压为 1 0 V,栅压为 1 2 V时 ,模拟得到的饱和漏电流接近 40 m A。计算结果与实验值符合较好。     

杂质不完全离化对SiC MOSFET的影响

在分析 Si C中杂质部分离化时 ,考虑了 Frenkel- Pool效应 ,通过求解 Si C MOS表面空间电荷区中的一维Poisson方程 ,提出了一个新的 Si C MOSFET反型层薄层电荷 (charge- sheet)数值模型 .对 Si C中杂质不完全离化的研究表明 ,杂质原子较大的离化能、高的掺杂浓度以及低温会使不完全离化的影响增强 ,对于 Si C MOSFET,杂质不完全离化的影响主要在亚阈区     

碳化硅MOSFET电学参数的电容-电阻法评估

阈值电压、栅内阻、栅电容是碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)的重要电学参数,但受限于器件寄生电阻、栅介质界面态等因素,其提取过程较为复杂且容易衍生不准确性。文章通过器件建模和实验测试,揭示了MOSFET的栅电容非线性特征,构建了电容-电阻串联电路测试方法,研究了SiC MOSFET的栅内阻和阈值电压特性。分别获得栅极阻抗和栅源电压、栅极电容和栅源电压的变化规律,得到栅压为-10V时的栅内阻与目标值误差小于0.5Ω,以及串联电容相对栅源电压变化最大时的电压近似为器件阈值电压。相关结果与固定电流法作比较,并分别在SiC平面栅和沟槽栅MOSFET中得到验证。因此,该种电容-电阻法为SiC MOSFET器件所面临的阈值电压漂移、栅极开关振荡现象提供较为便捷的评估和预测手段。     

基于ABM器件的SiC MOSFET建模研究

针对不同温度下SiC MOSFET模型精度不足的问题,提出一种基于模拟行为模型(ABM)器件建立SiC MOSFET模型的方法.分别对整体模型的沟道电流、导通电阻和栅漏电容部分进行改进,引入了阈值电压和跨导系数的温度调节函数,考虑了温度和栅源电压对导通电阻的影响,提出了无开关栅漏电容,建立了满足连续温度仿真的SiC M...     

n沟6H-SiC MOSFET阈值电压的温度特性模拟与分析

分析了n沟6H—SiCMOSFET的杂质不完全离化和SiO2—SiC界面存在大量界面陷阱等问题，研究了影响6H—SiCMOSFET器件阅值电压温度特性的诸因素。通过解析式计算和MEDICI软件模拟，得到了多种因素共同作用下的器件闪值电压的温度特性。研究表明，体内杂质的不完全离化、表面空间电荷层中的杂质离化程度和特定分布的界面电荷，对阅值电压的温度特性有显著的影响。     

基于分段拟合的SiC MOSFET模型优化方法

提出了一种基于分段拟合的SiC MOSFET模型优化方法.将表征静态特性的核心单元模型优化为分段模型,以使其能同时准确表征高、低栅压下器件的静态特性.同时,在模型分段处进行线性插值以保证模型函数的连续性,基于器件漏源支路元器件参数对拟合数据进行修正以提高模型表征参数的提取准确度.此外,为提高器件的动态模型准确度,增加了栅漏结电容模型函数的分段点,并给出了分段点选择方法.将优化前后栅漏结电容模型函数和静态仿真结果与测试获得的电容曲线、转移曲线和输出曲线进行对比,曲线匹配度较高,表明提出的优化方法显著提高了动态和静态模型的准确性.最后,搭建了SiC MOSFET开关特性测试平台,通过动态开关实验验证了模型优化方法的准确性.     

6H-SiCJFET的高温特性

分析和模拟了SiC JFET在高温下出现的栅电流。模拟结果反映出在温度高于700K以后栅电流对SiC JFET的影响将越来越显著,在此基础上该文建立起了一个6H-SiC JFET的高温模型。模型中采用了SiC的两极电离杂质模型和Caughey-Thomas方程。在300-773K的温度范围内,模型的模拟结果和实验数据相符。     

引入杂质激发态因素的SiC MOSFET反型层电荷模型

引入杂质激发态因素,建立新的SiC MOSFET反型层电荷模型.利用数值方法求解一维泊松方程,研究激发态对反型层电荷的影响.结果显示,在杂质激发态的作用下,反型层的电子面密度降低,并且杂质激发态主要影响SiC MOSFET的亚阈区特性.杂质激发态对SiC MOSFET反型层电荷的影响依赖于温度、掺杂浓度和杂质电离能.存在激发态影响最大的温度点,且其随掺杂浓度和电离能的增加而提高.     

SiC MOSFET栅极驱动电路研究综述

凭借碳化硅(SiC)材料的宽禁带、高击穿电场、高电子饱和速率和高导热性等优点,SiC MOSFET广泛应用在高压、高频等大功率场合。传统基于硅(Si)MOSFET的驱动电路无法完全发挥SiC MOSFET的优异性能,针对SiC MOSFET的应用有必要采用合适的栅驱动设计技术。目前,已经有很多学者在该领域中有一定的研究基础,为SiC MOSFET驱动电路的设计提供了参考。对现有基于SiC MOSFET的PCB板级设计技术进行了详细说明,并从开关速度、电磁干扰噪声以及能量损耗等方面对其进行了总结和分析,给出了针对SiC MOSFET驱动电路的设计考虑和建议。     

Optimization of the drift region of power MOSFET's with lateral structures and deep junctions

The electric field profile in the drift region of power MOSFET's with lateral structures and deep junctions has been found analytically. From the analysis, the best uniform surface doping density and the depth of the drift region in offset-gate power MOSFET's that introduces the minimum series resistance and sustains a given junction breakdown voltage is derived. Design guidelines for such MOSFET's are proposed. The comparison with computer simulation results has shown that it is reasonable for some practical structures.     

The influence of internal stresses in tungsten-gate electrodes on the degradation of MOSFET characteristics caused by hot carriers

The characteristic degradation of MOSFET's with tungsten-gate electrodes caused by hot carriers is shown to be enhanced by internal stresses in gate electrodes. These stresses introduce strains in silicon substrates under the edges of gate electrodes, which increases the number of surface states at the Si-SiO2interfaces. As a result, these internal stresses enhance the degradation of MOSFET characteristics due to hot carriers. A new technique for reducing the strains induced in the region under the gate electrodes is presented. With this technique (namely, annealing before patterning tungsten films for gate electrodes), the degradation of tungsten-gate MOSFET's can be decreased to a level compatible with that of conventional silicon gate MOSFET's.     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

FORWARD GATED-DIODE R-G CURRENT METHOD:A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.     

新结构MOSFET

和传统平面结构MOSFET相比，新结构MOSFET具有更好的性能(如改善的沟道效应(SCE)，理想的漏诱生势垒降低效应(DIBL)和亚阈值特性)和更大的驱动电流等。文章主要介绍了五种典型的新结构MOSFET，包括平面双栅MOSFET、FinFET、三栅MOSFET、环形栅MOSFET和竖直结构MOSFET。随着MOSFET向亚50nm等比例缩小，这些新结构器件将大有前途。     

A comprehensive study of hot-carrier instability in p- and n-typepoly-Si gated MOSFET's

A comprehensive comparison of hot-carrier instability between p- and n-type poly Si-gated MOSFET's is presented in this paper. The electron trapping and interface state generation in the 7 nm gate oxide of MOSFET's are investigated using uniform hot-electron injection from a buried junction injector (BJI) and channel-hot-carrier stress. From BJI experiments, electron trapping (instead of oxide trap generation) and interface state generation are shown to be the major effects of hot-electron injection. Electron trapping and interface state generation are found to be similar in both p- and n-type poly-Si gated MOSFET's. The dependences of interface state generation by hot electrons on oxide voltages and temperatures are observed to be similar between n- and p-type poly-Si gated MOSFET's. From the results of channel-hot-carrier stress on surface-channel n- and p-channel MOSFET's, it was also found that the channel-hot-carrier instabilities of p- and n-type poly-Si gated MOSFET's are comparable     

Dominant subthreshold conduction paths in short-channel MOSFET's

Conduction modes in off-biased n⁺-polysilicon gate MOSFET's of both polarities have been analyzed by two-dimensional device simulations. It was found that the dominant leakage paths in p-channel and n-channel enhancement devices occur in the bulk and at the surface, respectively, atV_{GS} = V_{BS} = 0. The control of these two distinct modes is the flatband voltage of the gate. The situation is exactly reversed when boron-doped polysilicon is used as the gate. Additionally, we showed that this physical insight can be readily gained by a quasi-two-dimensional analysis of the surface potential and its bending into the substrate. The leakage mode in short-channel MOSFET's with other gate material or with different interface properties generated by radiation or other stresses can thus be easily assessed. Subthreshold characteristics have been simulated for n⁺-polysilicon-gate low-threshold p-channel transistors having a p-type surface from boron counterdoping. The computed channel-length dependence is found to be in good agreement with measured data. Dominant leakage paths, in this case, remain in the bulk, while the surface holes from boron counterdoping are depleted by the flatband voltage. Since the common practice for reducing subthreshold leakage is to enhance substrate impurity concentration where punchthrough occurs, we therefore conclude that different strategies of process tailoring are required for MOSFET's of different gate material, surface polarity, and interface properties.     

γ—Radiation effects on MOSFET's fabricated with NMOS Submicrometer technology

In this letter, we report γ-radiation effects on MOSFET's fabricated with NMOS submicrometer technology. We have investigated the radiation sensitivity of n-channel MOSFET's with Leffvarying from 6 to 0.3 µm and with a gate oxide thickness of 250 Å. We observed that, for radiation doses ≤ 10⁴rad's, the threshold voltage shift is less than 75 mV and this shift is independent of the device geometry (even for Leff= 0.3 µm). A comparision has also been made between TaSi2gate MOSFET's and poly-gate MOSFET's. The deposition of TaSi2on poly/oxide/silicon structure does not decrease the radiation sensitivity of these MOSFET's. We have also compared MOSFET's fabricated with X-ray lithography and optical lithography. The X-ray lithography does not have a significant effect on the radiation sensitivity of these MOSFET's.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

深亚微米MOSFET热载流子退化机理及建模的研究进展

本文给出了深亚微米ＭＯＳ器件热载流子效应及可靠性研究与进展,对当前深亚微米ＭＯＳ器件中的主要热载流子现象以及由其引起的器件性能退化的物理机制进行了详细论述。不仅对热电子,同时也对热空穴的影响进行了重点研究,为深亚微米ＣＭＯＳ电路热载流子可靠性研究奠定了基础。本文还讨论了深亚微米器件热载流子可靠性模型,尤其是ＭＯＳ器件的热载流子退化模型。