Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications.As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure,and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.     

一种交叉互联的高可靠锁存器

现阶段随着CMOS工艺特征尺寸的减小,电路中可能会发生单粒子翻转（Single Event Upset,SEU）的敏感节点之间的距离在不断减小,发生一颗高能粒子引起多个节点同时发生翻转的事件概率正逐渐上升。为了提高电路的可靠性,基于抗辐射加固设计方法,提出了一种能够容忍两个节点同时发生翻转的锁存器。该锁存器以双输入反相器(Double-input Inverter,DI )单元作为核心器件,并且在 DI 单元之间采用了交叉互联的连接方式,减少了器件个数的使用。与传统的具有容错能力的锁存器相比,所提出的结构不仅具有良好的抗双点翻转能力,而且在功耗、延迟以及功耗延迟积（Power Delay Product,PDP）方面都有很大的优势。该结构可靠性高、性能优良,在提高芯片的可靠性方面具有重要意义,有实用价值。     

基于错误传播分析的SDC脆弱指令识别方法

单粒子软错误是高辐照空间环境下影响计算可靠性的主要因素.随着芯片晶体管数的快速增长,单粒子软错误的威胁日益严重.结果错误（silent data corruption, SDC)是单粒子软错误造成的一种故障类型.由于SDC是隐蔽传播的,SDC的检测是单粒子软错误防护的难点.寻找SDC脆弱指令是目前检测SDC的重要途径.现有方法需要进行巨量的错误注入,时间代价巨大.首先根据数据关联图建立了指令的数据依赖关系,研究了函数间和函数内部错误传播过程;进而推导出判定SDC脆弱指令的充分条件,提出了SDC脆弱指令识别方法,该方法在错误注入中依据充分条件推测潜在的SDC脆弱指令.实验表明,在保证较高准确率和覆盖率的前提下,时间代价显著减少.     

基于65nm工艺的SOC物理设计中的关键技术研究

随工艺的演进,集成电路发展已经进入超深亚微米阶段,芯片的成本、性能、功耗、信号完整性等问题将成为制约SOC芯片设计的关键问题。文章基于65GP工艺的实际项目模块级物理设计,在现超深亚微米下,对芯片的低功耗、congestion、信号完整性等后端物理设计等关键问题进行了细致研究,并提出了一些新方法和新思想,从而提高了signoff的文付质量,完成了tapeout要求。     

32 nm CMOS工艺的单粒子多点翻转加固锁存器设计

随着集成电路工艺不断改进,电荷共享效应诱发的单粒子多点翻转已经成为影响芯片可靠性的重要因素.为此提出一种有效容忍单粒子多点翻转的加固锁存器:低功耗多点翻转加固锁存器(low power multiple node upset hardened latch,LPMNUHL).该锁存器基于单点翻转自恢复的双联互锁存储单元(...     

基于Muller_C单元和DICE单元的抗辐照D触发器设计

随着工艺尺寸的缩减,单粒子翻转(SEU)和单粒子瞬态(SET)成为了深亚微米集成电路中备受关注的可靠性问题。本文基于Muller_C单元的静态电路和动态电路,设计了两种时域采样锁存器,并与DICE锁存器相结合,设计出了相应的既抗SEU又抗SET的D触发器(Dflip-flops,简称DFF)。通过三维TCAD混合模拟产生的SET,对两种D触发器版图后提取寄生参数的电路网表进行故障注入模拟,Hspice模拟的结果证明:两种DFF在有效抑制SEU的同时,还可以有效地抑制SET。与文献[1]中提出的既抗SEU又抗SET的DFF相比,本文中设计的DFF面积较小,500MHz下动态功耗和静态功耗均有所降低,其中一个DFF的建立时间优于文献[1]中的DFF。     

基于单片SRAM的EDAC电路设计

在航天应用中,为了减少单粒子翻转效应的影响,星载计算机的RAM存储单元采用检错纠错(EDAC)设计。本文介绍了EDAC原理,并对EDAC电路组成进行改进,将数据和校验存储在一片64Kx8的SRAM中,通过FPGA内部逻辑实现EDAC功能和RAM读写控制,增加了纠错回写和纠错计数功能,并提供测试验证EDAC功能的方法。     

星载数据加密容错研究

在空间辐射环境中,单粒子反转效应(SEU)会导致星载系统存储器逻辑位发生翻转,且无法单纯依赖硬件措施完全消除,又由于卫星通信加密设备在大多数加密模式下具有错误扩散特性,星载数据加密设备的SEU软故障会导致批量数据不可用.针对星载数据加密过程的SEU影响问题,设计了基于奇偶校验码的星载数据加密过程检错算法和基于海明码的星载数据加密过程纠错算法,该容错方案可以有效降低SEU对星载数据加密过程的影响,提高星载数据加密的可靠性.通过大量图像数据仿真实验结果表明,提出的容错方案对星载数据加密过程可靠性的提高率与位出错概率成反比,有较好的空间适应性.     

Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process

Through revising the process of charge collection for reversed drain-bulk junction,a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS.The model can capture the plateau effect,and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation.Considering the case of connecting load,it is still valid.For combination and sequential logic circuits,the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.     

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

With the shrink of the technology into nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset (SEU), especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code (SCAC) in our previous work, joins crosstalk avoidance code (CAC) and error correction code (ECC) together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.     

基于安时积分和粒子滤波修正的锂电池SOC估计

针对安时积分（ AH）法的累积误差问题和卡尔曼滤波算法对系统噪声的限制,提出了粒子滤波（ PF）修正安时积分误差的方案,并基于钴酸锂电池测试数据和电池等效电路模型,对算法进行仿真验证。通过与传统的AH和卡尔曼滤波法对比得出：基于AH和PF修正的方法荷电状态（ SOC）估计效果较好,平均误差与标准误差均控制在2%以内。     

一种检测程序控制流故障的方法

本文介绍一种在容错处理器中实现控制流故障检测的方法。处理器的容错机制是通过修改超标量体系结构,利用时间冗余技术实现的。处理器支持两个指令流并发执行,本文提出的控制流检测算法是通过比较两个时间冗余的指令流的执行结果实现的,与同类实现方案相比,此方法可以进一步节省硬件资源以及额外的处理器执行时间。     

基于工况特性的电动汽车蓄电池组SOC与SOH在线智能识别与评价方法研究

蓄电池组SOC和SOH是电动汽车电池管理和能量管理的关键参数,受单体电池特性、蓄电池组一致性和均衡技术等因素影响,不易建立准确计算模型.基于电动汽车日常行驶工况统计特性提出一种改进的Ah积分法计算蓄电池组SOC和SOH,该方法采用工况容量与等效工况电流根据Peukert方程实现稳态容量修正,同时采用模糊逻辑实现放电率波动对容量的动态修正;提出采用单体统计特性建立状态评价矩阵表征蓄电池组状态的全面评价方法;最后通过对比仿真计算分析验证了所提方法的合理性和实用性.     

FOM – a MATLAB toolbox of first-order methods for solving convex optimization problems

This paper presents the FOM MATLAB toolbox for solving convex optimization problems using first-order methods. The diverse features of the eight solvers included in the package are illustrated through a collection of examples of different nature.     

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Heavy ion experiments were performed on D flip-flop （DFF） and TMR flip-flop （TMRFF） fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU cross- section compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2~ harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.     

高可靠8051微处理器的设计与实现

本文介绍了一款高可靠8051(HR8051)的设计与实现。在一款现有高性能8051微处理器体系结构的基础上,针对单粒子翻转事件(SEU),应用各种可靠性增强技术,如时空三模冗余(ST-TMR)、控制流检测、安全状态机等,并对可靠性增强后的处理器进行故障注入,以验证其可靠性增强效果。故障注入结果表明,采用了可靠性增强技术后,处理器的可靠性有了很大的提高。     

深亚微米CMOS SRAM SEE特性及加固技术研究

在空间环境甚至在地面环境中,受高能粒子等多种因素的的影响,深亚微米COMS SRAM很容易发生单粒子事件(single event effects,SEE),使得COMSSRAM中的存储数据发生翻转甚至直接将器件烧毁.对深亚微米CMOS SRAMSEE特性与器件基本存储结构、数据读写速度、集成度、供电偏压等的关系进行了研究,同时从器件级和系统级两个层面时CMOSSRAM抗SEE加固方法进行了研究,最后给出了一种基于高可靠性反熔丝型FPGA硬件实现的系统级抗SEU设计,该系统可以纠正单个字(32bit)及其校验位(7bit)数据的一位错,检测两位错,该设计具有强实时、高可靠性的特点,已通过了各类空间环境试验.     

基于简化电阻电容电路的单粒子效应应用研究

随着器件尺寸缩小至纳米级,微观粒子对半导体器件的影响变得越来越明显。器件可靠性的研究近年来逐渐引起了人们的重视,开展了很多相关研究。以研究单粒子翻转效应为核心,在传统混合仿真的基础上,采用简化RC电路模型对简化电路的应用进行研究,总结了电阻和电容值变化对等效电路中敏感节点处电学特性变化的规律,探究了使用Id Vd曲线判断单粒子翻转的准确性,提出了在研究临位翻转时,通过单次实验即可有效预测临位翻转情况的方法。根据实验所得的电压电流曲线图形特点对它们进行分类,从而判断临位翻转。通过模拟实验与预测结果比对,两者的结果相符,预测有较高准确性。     

A Robust and Power-Effcient SoC Implementation in 65nm

Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.     

SEU的二维数值模拟

本文阐述了单粒子效应原理和损伤机理,对MEDICI软件进行了简要介绍。运用MEDICI软件分别对体硅和SOI(Silicon-On-Insulator)衬底材料进行CMOS SRAM的SEU(Single -Event Upset)模拟实验,得出实验结果,并对实验结果进行分析,证明了SOI材料有良好的抗辐射加固特性,体现出SOI材料的优越性。