An 8-bit 80-Msample/s pipelined analog-to-digital converter withbackground calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology     

An 8-bit 100-MHz full-Nyquist analog-to-digital converter

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation     

An 8-bit 12.5-GSample/s SiGe ADC

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm² and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process.     

A pipelined 5-Msample/s 9-bit analog-to-digital converter

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.     

A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency

This article presents a wideband calibration-free 8-bit analog-to-digital converter (ADC) with low latency. The ADC employs a two-stage cascaded folding and interpolating architecture. A high-linearity and wideband track-and-hold amplifier combined with a low-parasitic-capacitance folding amplifier is employed to improve the performance. A binary-ROM with “keep-alive” current is proposed to guarantee no miscode when large bit-rate is input. When the sampling frequency is 1.5 GHz, the ADC achieves +0.29/?0.20 LSB DNL and 0.90 LSB INL. The ADC’s effective-number-of-bit and spur-free-dynamic-range are 7.0 bit and 51.8 dB respectively at 230 MHz input. The effective-resolution-bandwidth exceeds the second Nyquist zone up to 1.8 GHz. All of this makes this ADC suitable for wideband digital receiver system.     

An 8-bit flash analog-to-digital converter with an array of redundant comparators

The circuit design and the topology of an 8-bit analog-to-digital converter (ADC) are presented. It is shown that the differential nonlinearity can be reduced by using three comparators and a majorizing element for formation of each bit of the thermometric code. Computer simulation and measurements of reference ADC chips fabricated using the UMC 180-nanometer CMOS technology confirmed the operability of the proposed design. A power consumption of 93 mW, an effective number of bits of 5.8, and a differential nonlinearity of 0.03 bits have been obtained     

A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter

A four-bit silicon bipolar analog-to-digital converter (ADC) which is operational at the full Nyquist input frequency up to 1 Gsample/s (Gs/s) is discussed. The effective bit number at 1 Gs/s reduces to 3.5 bits on Nyquist conditions. The 3-dB large-signal analog bandwidth is 800 MHz and the maximum sampling rate reaches 2 Gs/s and beyond. The converter is built up by stacking of two three-bit subcircuits. The ADC architecture relies on a balanced structure mixing conventional flash-converter elements with analog encoding. Total power consumption is 2.4 W. Standard silicon bipolar technology is used without self-alignment     

An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.     

A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter

A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3-μm, CMOS technology. Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize the overall cost. The prototype converter requires 3400 mil², and consumes 15 mW     

一种采用数字前端校正技术的8位超高速时间交叠折叠/内插模-数转换器

本文呈现了一种0.35微米BiCMOS工艺下采样率为2GSPS的8位模数转换器。此ADC采用独特的折叠/内插算法,利用双通道间的时钟交叠复合技术,可以获得2GSPS的采样率。对S/H电路的失调误差与增益误差、前置放大器的失调误差、通道间的增益误差与时钟相位误差进行校正。测试结果表明,芯片在自校正工作状态下,模拟输入为484MHz时,ENOB为7.32位,而在Nyquist输入频率下ENOB为7.1位。     

2-bit 1-Gsample/s electro-optic guided-wave analogue-to-digital convertor system

An electro-optic analogue-to-digital convertor system has been demonstrated at 1 Gsample/s. This system has been tested with low-frequency waveforms and by means of a beat-frequency technique with a 499 MHz test signal. Digital outputs are slowed in time and then fed into 125 MHz digital-toanalogue convertors which accurately reconstruct the beat signal, proving the compatibility of electra-optic signal processing with digital circuits.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

Optimal design of a low-loss 2-bit electrooptic analog-to-digital converter

The structure of the optical waveguide of 2-bit electrooptic A/D converter with proton-exchange micro prisms is optimized by the finite-difference beam propagation method （FD-BPM） The electrode parameters of the converter are optimized by conformal mapping. The optimal parameters are a half- wave voltage of Vπ = 4.5 V and a bandwidth of △f = 1.4 GHz. A normalized transmitted power of 69.75% is obtained by FD-BMP and the output waveguide gap is 300 μm.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold

A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.     

An 8-bit parasitic-insensitive switched-capacitor A/D converter

An algorithmic A/D converter (ADC) is presented which employs switched capacitors. The ADC is insensitive to parasitic capacitances and op-amp offset voltages. Capacitor ratio-mismatch errors and charge injection errors are investigated. System level computer simulations are included to support the theory. The technique is suitable for 8-bit A/D conversion using present CMOS technology.     

An 8-bit high-speed CMOS A/D converter

An 8-bit high-speed A/D converter has been developed in a 1.5-/spl mu/m bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimized. High speed (30 MS/s) and low power consumption (60 mW) have been obtained. Computerized evaluations such as the histogram test and the fast Fourier transform test have been used to measure dynamic performance. The linearity error in dynamic operation is less than /spl plusmn/1 LSB. Signal-to-peak-noise ratio is 40 dB at a sampling rate of 14.32 MS/s and an input frequency of 1.42 MHz.     

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter usinga 70-ps silicon bipolar technology with borosenic-poly process andcoupling-base implant

A dual 4-b analog-to-digital converter (ADC) with Nyquist operation to 2 gigasamples/second (Gs/s) and -29-dBc distortion at 1 GHz is presented. A novel evaluation method using an integral digital-to-analog converter is introduced. A trench-isolated, self-aligned, double-polysilicon bipolar process is used for the chip fabrication. This ADC has a resolution of 3.73 effective bits at 1-GHz analog input signal, without the use of a preceding sample-and-hold. Low-frequency untrimmed distortion is -48 dBc (not including quantizing error), and is independent of the sample rate of 2 Gs/s     

1-GHz, 16-mW, 2-bit analog-to-digital GaAs converter

Dislocation-free wafers combined with enhancement-mode MESFETs arranged in an original design have been used to realize ultra-high-speed and accurate compensators and 2-bit converters. A 1-GHz sampling rate, associated with 16-mV power consumption, has been demonstrated and the accuracy results indicate that a 4- or 5-bit A-D converter could be designed.     

Toward a 100-Gsample/s photonic A-D converter

We propose a 100-Gsample-per-second (GSPS) real time photonic analog-to-digital converter architecture and demonstrate the 100-GSPS photonic sampling and 1:8 time-division optical demultiplexing required to implement such a converter. The high-speed demultiplexing is achieved with a lithium niobate intensity modulator-based serial-parallel converter. Experimental results are presented indicating the potential for >4-bit performance in a fully implemented analog-to-digital conversion system