Extraction of collector resistances for device characterization and compact models

A methodology for the extraction of a bipolar transistor collector resistance from its output characteristics using the Forced-Beta Method has been demonstrated. The presented extraction methodology eliminates the need for additional measurements in the evaluation of collector resistances and allows reuse of the existing standard output characteristics data. The method is particularly suitable for compact modeling and technology characterization from high-frequency transistor test structures with no separate substrate contacts.     

New integral representations of circuit models and elements for the circuit technique for semiconductor device analysis

New integral representations of the distributed and one-lump circuit models and their circuit elements, accurate to mesh-size cubed (Δx)³ using the trapezoidal approximation, are presented for large-signal transient, D.C. and small-signal numerical and analytical simulations of semiconductor devices.     

Investigation of compact models for RF noise in SiGe HBTs by hydrodynamic device simulation

A comprehensive investigation of the SPICE and unified compact noise models is performed by comparison with the more fundamental hierarchical hydrodynamic device model. It is shown that the rather simple SPICE and unified compact noise models yield good results for frequencies up to 10 GHz for state-of-the-art SiGe HBTs with a low base resistance. The base noise resistance, a key parameter of the compact noise models turns out to be independent of frequency and bias. It can be well estimated based on the sheet resistance of the intrinsic and extrinsic base or with the modified circle-fit method. The unified model, which in comparison to the SPICE model considers in addition the finite transit time of shot noise, is found to be somewhat more accurate than the SPICE model, especially at higher frequencies and collector currents. But this is achieved at the expense of a transit time parameter which cannot be determined without accurate and detailed noise measurements or physics-based numerical simulations.     

Bio-inspired compact cell circuit for reaction-diffusion systems

A bio-inspired MOS cell design for reaction-diffusion systems with corresponding single-layer cellular neural network (CNN) implementation is presented. The resulting network layer is introduced and approximate theoretical analysis of its certain dc characteristics is given. A test chip which includes a two-dimensional array of 10 /spl times/ 9 cells is fabricated. The test chip also houses stand-alone modified cells which employ thick-oxide poly2 gate MOSFETs where the inherent high threshold characteristic is used for the design. Both the cell circuit design and the resulting network are very compact and easily implementable with available technologies. The network layer is capable of trigger wave propagation and can also be used as a compact building block for more general and multilayer reaction-diffusion (RD)-CNN designs. The wave propagation across the network and nonlinear I-V characteristics of the separate cells with thick-oxide MOSFETs are demonstrated via measurement results.     

Assessment of approximate balance equation transport models used for submicron silicon device modelling

The common approximations found in literature for the balance equation method used for non-stationary submicron device simulation are presented and discussed. To assess different approximations, the full balance equation model is solved numerically solved for the n⁺-i-n⁺ submicron silicon structure where nonstationary transport effects eventually take place. The results obtained from the derived approximate models applied to the same silicon structure are compared with those obtained from the full model. In all cases, empirical formulae for momentum and energy relaxation times are used to clarify only the effect of approximations on the simulation results.     

Physically based models of electromigration: From Black’s equation to modern TCAD models

Electromigration failure is a major reliability concern for integrated circuits. The continuous shrinking of metal line dimensions together with the interconnect structure arranged in many levels of wiring with thousands of interlevel connections, such as vias, make the metallization structure more susceptible to failure. Mathematical modeling of electromigration has become an important tool for understanding the electromigration failure mechanisms. Therefore, in this work we review several electromigration models which have been proposed over the years. Starting from the early derivation of Black’s equation, we present the development of the models in a somewhat chronological order, until the recent developments for fully three-dimensional simulation models. We focus on the most well known, continuum physically based models which have been suitable for comprehensive TCAD analysis.     

GaAsMESFET小讯号等效电路参数提取

讨论了一种提取ＧａＡｓＭＥＳＦＥＴ小讯号等效电路参数的方法，本方法可直接决定外部和本征小讯号参数。所得到的等效电路的Ｓ参数计算值与测量值基本吻合。     

Wideband compact antenna for K-band applications

A compact coupled microwave active antenna is presented. This antenna is proximity fed, and consists of a square radiating element array on a polymer dielectric layer. The compactness of the antenna is obtained through technological optical processes and the parasitic patch phenomenon which increases the bandwidth     

A physical compact model of DG MOSFET for mixed-signal circuit applications - part II: Parameter extraction

For pt. see ibid., vol. 50, no. 10, p. 2135 (2003). Based on the physical double-gate MOSFET model described in Part I, we present a systematic parameter extraction methodology that avoids parameter interdependence between different physical effects whenever possible. Several extraction schemes are compared for precise modeling of small-signal and large-signal characteristics. The physical model and the extraction methodology are verified through the reproduction of the simulated drain current, incremental drain resistance, and transconductance per unit current, which are parameters of particular interest to mixed-signal circuit designs.     

A compact antenna for ultrawide-band applications

A novel compact and ultrawide-band (UWB) antenna is presented in this paper. The basis for achieving such an UWB operation is through proper magnetic coupling of two adjacent sectorial loop antennas in a symmetrical arrangement. A large number of coupled sectorial loop antennas (CSLA) with different geometrical parameters are fabricated and their measured responses are used to experimentally optimize the geometrical parameters of the antenna for achieving the maximum bandwidth. Through this optimization process an antenna with a VSWR of lower than 2.2 (S/sub 11/<-8.5 dB) across an 8.5:1 frequency range is designed. The maximum dimension of this antenna is smaller than 0.37/spl lambda//sub 0/ at the lowest frequency of operation and provides an excellent polarization purity. Furthermore, the antenna exhibits a relatively consistent radiation pattern. Modified versions of the CSLA are also designed to reduce the overall metallic surface and weight of the antenna while maintaining its wide-band characteristics. This allows modifying its dimensions to design low frequency light-weight UWB antennas.     

Physically realistic fault models for analog CMOS neural networks

A general methodology for the development of physically realistic fault models for VLSI neural networks is presented. The derived fault models are explained and characterized in detail. The application of this methodology to an analog CMOS implementation of fixed-weight (i.e., pretrained), binary-valued neural networks is reported. It is demonstrated that these techniques can be used to accurately evaluate defect sensitivities in VLSI neural network circuitry. It is also shown that this information can be used to guide the design of circuitry which fully utilizes a neural network's potential for defect tolerance     

An analog trimming circuit based on a floating-gate device

The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed. A simple trimming circuit based on this principle and delivering a differential current is described. Experimental results of a differential difference amplifier (DDA) containing two such circuits are given. After trimming, an offset voltage of 10 μV and a nonlinearity of 0.1% are achieved. Other analog circuits based on floating-gate elements like adjustable voltage sources and transconductances have been realized. Because they can be electrically reprogrammed, a wide range of applications, for example in neural nets, are possible     

Standardizing compact models for IC simulation

The idea of standard compact (SPICE-like) model equations has gained support recently throughout the semiconductor industry. In the past, compact models have been developed independently either by a single company or by a university or research group. These models have lacked diverse technology coverage and normally were not fully tested or productized. The concept of standardization is embraced by the semiconductor industry in several other areas, yet simulation has lagged behind due to the difficult notion of standardizing software. In this article, the idea of a standard compact model will be described as well as the industry consortium supporting the standardization effort     

Thermal parameter extraction for bipolar circuit modelling

A practical method is presented for extracting the thermal spreading resistance of BJTs, which is needed for accurate circuit simulation. The method uses the output resistance as the temperature sensitive parameter. Measurements can be made in the time or frequency domain.<>     

New technique for semiconductor device modelling

A transient model has been developed for use with microwave semiconductor devices. Charge transport is by particles moving under the influence of the electric field in a self consistent time-stepping procedure. The motion of each particle is governed by its momentum and energy using the relaxation time approximation.     

Study of compact antenna for UWB applications

A novel miniature antenna design for ultra-wideband (UWB) applications is presented. The proposed compact antenna is achieved by exploiting a quasi-self-complementary structure along with a tapered radiating slot. The optimal design of this type of antenna can offer an ultra-wide 10 dB impedance bandwidth with reasonable radiation properties. It also exhibits very small dimensions, 19 x 16 mm in physical size, and 0.19 l in electrical size. Good agreement is obtained between simulated and measured antenna characteristics.     

A physically based compact device model for fully depleted andnearly fully depleted SOI MOSFET

A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device model suitable for analog as well as digital application has been proposed. It is an all region model. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, we have given careful consideration to parasitic source/drain resistance, Drain Induced Conductivity Enhancement (DICE) effect, floating body effect, self-heating and model continuity. A single parameter set is used for a large set of device dimensions except threshold voltage and parasitic source/drain resistance due to silicon film thickness variations. The accuracy of the model is validated with experimental data using NMOS FDSOI devices and found to be in good agreement     

A COMPACT QUADRATURE FEEDING CIRCUIT FOR CIRCULARLY POLARIZED ANTENNA

A novel compact quadrature feeding circuit for a circularly polarized antenna is described. The equivalent circuit method in microwave network theory is used and the conventional directional coupler is converted to a new quadrature feeding circuit. This feeding circuit has the same characteristics as the conventional directional coupler but its size is only about one fourth of that of the latter. The formulas for designing the feeding circuit are given. The optimized results obtained by using the software ENSEMBLE are also reported.     

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.