Impact of nonuniform graded dopant profile in polysilicon gate on gate leakage current

In a MOSFET, a nonuniform, graded vertical dopant profile in the polysilicon gate causes a potential drop at the polysilicon/oxide interface. In this paper, the effect of this potential drop on the gate leakage current has been evaluated for the first time. The extent of variations of this affected gate leakage current with gate oxide thickness, gate length, and gate and drain bias conditions have been assessed with device simulation for an nMOS at 0.13 /spl mu/m low-voltage process. The results provide a guideline to the severity of this effect from the point of view of device and circuit operation and standby power consumption.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

A monolithic IGBT gate driver for intelligent power modules implemented in 0.8 μm high voltage (50 V) CMOS process

This paper discusses the design and implementation of a monolithic IGBT gate driver for intelligent power modules (IPMs). The objective of this work is to design and implement a monolithic IGBT gate driver IC with efficient protection functions in a high-voltage (50 V) 0.8-μm CMOS process. The gate driver is designed for medium power applications, such as home appliances. It includes low-voltage logic, 5-V logic regulator, analog control circuitry, high-voltage (50 V) high-current output drivers, and protection circuitry.     

A 0.5–7.5 GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18- μm CMOS Technology

A fully differential low-voltage low-power downconversion mixer using a TSMC 0.18-mum CMOS logic process is presented in this letter. The mixer was designed with a four-terminal MOS transistor, the radio-frequency (RF) and local-oscillator signals apply to the gate and bulk of the device, respectively while the intermediate frequency (IF) signals output was from the drain. The mixer features a maximum conversion gain of 5.7dB at 2.4 GHz, an ultra low dc power consumption of 0.48 mW, a noise figure of 15 dB, and an input IP of 5.7 dBm. Moreover, the chip area of the mixer core is only 0.18 times 0.2 mm². The measured 3-dB RF frequency bandwidth is from 0.5 to 7.5 GHz with an IF of 100 MHz, and it is greatly suitable for low-power in wireless communication.     

ST7538接口电路设计及其在智能家居上的应用

设计了基于ST7538电力线载波芯片的低压电力线载波通信接口电路,对接口电路中的耦合保护放大电路工作原理作了分析;对ST7538在智能家居上的应用作了设计,并通过实验验证了该设计。     

A large-area power MOSFET designed for low conduction losses

A new power MOSFET has been fabricated that conducts 75 A with an on-state resistance of 0.012 Ω and blocks 60 V. The device may be used as a low-loss synchronous rectifier in efficient high-frequency power supplies or as a high-current power switch in applications such as emitter switching. The device design criteria include obtaining the largest possible fraction of the ideal blocking voltage and obtaining the minimum on-State resistance. Efficient utilization of the device area requires smaller feature size and shallower junction depths for low-voltage power MOSFET's than for high-voltage ones. The device reported on is 300 mils on a side and contains over 60 000 MOSFET cells in parallel. It has a gate width of more than 4 m. This device is larger and more complex than any previously reported power MOSFET. It provides an example of how power device processing techniques are approaching those of LSI circuit technology.     

一种采用单信号控制的新型高压高低侧功率器件

Novel high-voltage, high-side and low-side power devices, whose control circuits are referred to as the tub, are proposed and investigated to reduce chip area and improve the reliability of high-voltage integrated circuits. By using the tub circuit to control a branch circuit consisting of a PMOS and a resistor, a pulse signal is generated to control the low-side n-LDMOS after being processed by a low-voltage circuit. Thus, the high-voltage level-shifting circuit is not needed any more, and the parasitic effect of the conventional level-shifting circuit is eliminated. Moreover, the specific on-resistance of the proposed low-side device is reduced by more than 14.3% compared with the conventional one. In the meantime, integrated low-voltage power supplies for the low-voltage circuit and the tub circuit are also proposed. Simulations are performed with MEDICI and SPICE, and the results show that the expectant functions are achieved well.     

High-efficiency enhancement-mode power heterojunction FET with buried p/sup +/-GaAs gate structure for low-voltage-operated mobile applications

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p/sup +/-n junction gate structure for low-voltage-operated mobile applications. The buried p/sup +/-GaAs gate structure effectively reduced on-resistance (R/sub on/) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p/sup +/-gate HJFET exhibited a low R/sub on/ of 1.4 /spl Omega//spl middot/mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.     

A simplified low-voltage smart power technology

A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate     

Design of a 60-V 10-A intelligent power switch using standard cells

A small, low-cost, intelligent power switch (IPS) for use in automotive applications is described. The chip integrates a 60-V 30-mΩ power device with a comprehensive set of protection functions using a mixed-voltage standard cell methodology and only 11 mask layers     

An intelligent power IC with double buried-oxide layers formed bySIMOX technology

A device structure for an intelligent power LSI composed of a vertical power MOSFET and a control CMOS LSI on a single chip is discussed. The distinctive feature of the device structure is that double buried-oxide layers formed by SIMOX technology are utilized to electrically protect the CMOS LSI from the high voltage applied to the power MOSFET. An evaluation of the electrical characteristics of an intelligent power IC and its components fabricated on a trial basis for automotive applications verifies the usefulness of the device structure     

High-frequency performances of a partially depleted 0.18-μmSOI/CMOS technology at low supply voltage-influence of parasiticelements

This paper shows for the first time the high-performances of a partially depleted 0.18-μ_m technology at low supply voltage. The SOI technology uses a standard digital process with a TiSi ₂ salicided polysilicon gate and a low dose SIMOX substrate. The process does not include any specific feature like T-gate, or high-resistivity SOI substrate. At 1 V, and 2 GHz the current gain and the unilateral power gain are higher than 15 dB for both 0.18 μm gate length NMOS and PMOS transistors. At 1.5 V, the 0.18-μm NMOS and PMOS show a transition frequency of, respectively, 51 GHz and 23 GHz and a maximum oscillation frequency of 28 GHz and 13 GHz. These results have been obtained with an optimized transistor geometry to reduce the influence of the access resistances. The high-frequency potential of this 0.18-μm SOI technology demonstrates the possible integration of microwave functions with digital circuits on a single chip for low-power, low-voltage applications like wireless telecommunication     

Polyimide/polyvinyl alcohol bilayer gate insulator for low-voltage organic thin-film transistors

In this paper, we report the fabrication of a polyimide/polyvinyl alcohol (PVA) bilayer gate insulator for low-voltage organic thin-film transistors (TFTs). The introduction of a PVA layer to form a bilayer structure improves the dielectric and insulating properties of the gate insulator. Organic TFTs with 150 nm-thick polyimide and PVA gate insulators were inactive at low operation voltages below 5 V. Conversely, organic TFTs with 150 nm-thick polyimide/PVA bilayer gate insulators exhibited excellent device performances. Our results suggest that the introduction of a PVA layer with a high dielectric constant could be a simple and efficient way to improve the device performance of low-voltage organic TFTs.     

一种用于TFT-LCD液晶显示的片内门宽调制控制器的设计

为了防止在液晶显示面板上发生闪烁和减小栅驱动器的馈通现象,设计了一种基于升压型DC-DC和电荷泵的用于TFT-LCD液品显示的片内门宽调制控制器.该控制器能减小液品显示功耗,减少栅走线和液晶面板之间的耦合效应,其输出延时可调并输入到栅驱动器中,从而避免液晶显示设备错误的显示.采用该门宽调制器的基于电流模PWM升压型DC-DC和电荷泵的芯片已在UMC 0.6μm BCD工艺线投片,DC-DC的效率高达93%,可调电荷泵输出电压为10～30V,测试结果证明该门宽调制控制器电路工作良好,其面积为0.3mm2,静态电流小于1μA.     

Improved thermal management of low voltage power devices with optimized bond wire positions

This paper focuses on optimization of bond wire positions as a method to improve thermal management of power semiconductors. For this purpose, robustness of a new low-voltage MOSFET generation with an optimized multiple bond wire arrangement and device shape is compared to an older device design with lower number of bond wires. 2D electrical simulation is used to evaluate the lateral distribution of power dissipation due to the gate voltage de-biasing effect. 3D thermal finite element simulation and infrared thermography measurements are employed to analyze the corresponding surface temperature distribution. Finally, tests under extreme single pulse short-circuit conditions demonstrate the effectiveness of thermal management for improving robustness in automotive applications.     

One-pot surface modification of poly(ethylene-alt-maleic anhydride) gate insulators for low-voltage DNTT thin-film transistors

This study investigates the one-pot surface modification of poly(ethylene-alt-maleic anhydride) (PEMA) gate insulators crosslinked with 1,5-naphthalenediamine (1,5-NDA) for enhancing the device performance of low-voltage dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) organic thin-film transistors (OTFTs). Surface properties of the PEMA gate insulator could be easily modified by adding poly(maleic anhydride-alt-1-octadecene) (PMAO) to the coating solution. The surface energy of the gate insulator is strongly correlated with the growth of organic semiconductors and the charge carrier transport at the interface between the semiconductor and gate insulator. The results indicate that the device performance of low-voltage DNTT OTFTs can be improved by one-pot surface modification of the PEMA gate insulator.     

微波大功率SiC MESFET及MMIC

利用本实验室生长的4H-SiC外延材料开展了SiC MESFET和MMIC的工艺技术研究.研制的SiC MESFET采用栅场板结构,显示出优异的脉冲功率特性,20 mm栅宽器件在2 GHz脉冲输出功率达100 W.将四个20 mm栅宽的SiC MESFET芯片通过内匹配技术进行功率合成,合成器件的脉冲功率超过320 W,增益8.6 dB.在实现SiC衬底减薄和通孔技术的基础上,设计并研制了国内第一片SiC微波功率MMIC,在2～4 GHz频带内小信号增益大于10 dB,脉冲输出功率最大超过10 W.     

A 920 gate DSA MOS masterslice

A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.     

A new high-density low-voltage SSIMOS EEPROM cell

An efficient low-voltage EEPROM cell is described which occupies an area of 135 µm²when fabricated with 3-µm CMOS technology. To charge and discharge the floating gate, the device relies on Fowler-Nordheim tunneling of electrons between the floating gate and a narrow window of the device channel region. In addition, the control gate is positioned so as to shield the remaining portion of the floating gate from the substrate. The cell can be programmed in 10 ms with a nominal WRITE voltage of 16 V and an ERASE voltage of 12 V. The WRITE/ERASE endurance of the cell is in excess of 10⁶cycles, and the data retention has been shown to be greater than 10 years at 125°C.