Reliability and routability consideration for MCM placement

This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.     

Reliability and wireability optimizations for chip placement on multichip modules

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.     

Thermal analysis for indirect liquid cooled multichip module using computational fluid dynamic simulation and response surface methodology

This paper demonstrates the application of computational fluid dynamic (CFD) simulation and response surface methodology (RSM) in analyzing the thermal performance of a high input/outputs, seven chips, indirect liquid cooled multichip module which will be applied in a kind of supercomputer. A series of similar experiments and corresponding CFD simulations are conducted firstly to evaluate the validity of CFD simulation method and determine the interfacial thermal resistance of thermal grease iteratively, and then a three-dimensional CFD model is established to investigate the heat transfer and fluid flow of the multichip module. Based on the CFD model, the individual effects of factors such as thermal conductivity of the thermal interface material and thermal grease, thickness of the chips, space between chips, solder bump patterns, solder ball patterns, flow velocity and liquid inlet temperature on the thermal performance of the module are studied with one-factor-at-a-time experimentation, and after that, four significant factors are selected to establish a response surface model of the maximum temperature of the module with central composite design based RSM and analysis of variance.     

Evaluation of Thermal Resistance Matrix Method for an Embedded Power Electronic Module

Thermal characterization provides data on the thermal performance of electronic components under given cooling conditions. The most common thermal characterization parameter used to characterize the behavior of electronic components is the thermal resistance. In this work, experiments are conducted to obtain thermal characterization data for different chips in a multichip package. Using this data, it is shown that the assumption of a linear temperature rise with input power is valid within the expected range of operation of the electronic module. Secondly, the applicability of a resistance matrix superposition methodology to the packaging structure of an integrated power electronic module is evaluated. The temperatures and the associated uncertainties involved in using the resistance matrix superposition method are compared to those obtained directly by powering all chips. It is shown that for any arbitrary power losses from the chips, the resistance matrix superposition method can predict the temperatures of a multichip package with reasonable accuracy for temperature rise up to 50degC.     

基于FPGA的芯片功能性验证自动化实现

针对传统半导体设计流程中对MCU芯片进行功能性验证时涉及到多个芯片之间的互联,手工操作连接十分烦琐且易出现错误,介绍了一种基于FPGA的MCU引脚自动互联的设计与实现.介绍了MCU模块功能性验证自动化实现的概念,从硬件逻辑角度给出了一种解决方法,并且从FPGA模块设计、功能仿真和系统实现等方面,证明了新的测试方法不但降低了人为操作错误的可能性,而且提高了模块功能验证的覆盖率和验证效率,大大缩短了产品的上市时间.     

Test structures for MCM-D technology characterization

In this paper we present a set of classic and novel test structures addressed to fully characterize multichip module (MCM) technologies. The structures have been implemented and fabricated in our D-type, flip-chip, ball grid array, silicon substrate technology. In this technology, a silicon chip is used as a substrate on which other commercial chips are flipped and soldered by a screen-printing method. These complex technologies have specific test problems that are solved with this approach. We have specially focused on the measurement of the effects of wafer rerouting on CMOS parameters, the chip-to-chip ball contact resistance, thermal behavior, yield, and reliability of the technology. Experimental results are shown, proving that this methodology is suitable for our technology and can also be applied to other different MCM technologies     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

A Force-Directed-Based Optimization Scheme for Thermal Placement Design of MCMs

Thermal management becomes exceptionally critical to both the reliability and operation performance of electronic packages, particularly for multichip modules (MCMs), as packaging and power densities continue increase while packaging dimension continues decrease. The underlying goal of the study is to pursue the minimum system temperature design of MCMs containing a number of chips of equal and/or unequal power through the optimal chip placement design. To deal with the thermal design problems, an effective indirect optimization approach that integrates a modified force-directed (FD) thermal model, a finite-element (FE) technique and an exterior penalty method (EPM) is proposed. In the modified FD thermal model, a novel representation of the repulsive and attractive forces is proposed, and the sum of these forces in the design system, representing the total system chip junction temperature, constructs the objective of the optimization problems. Together with some geometry constraints, the constrained optimization problems are formed, and furthermore, transformed into unconstrained optimization problems using an EPM. The solution of the optimization problems is sought through a direct, iterative search scheme with two proposed placement strategies. The alternative goal of the study is to address the feature and feasibility of these two proposed placement strategies for the current problems. The applicability of the proposed optimization approach is demonstrated through several design applications, and their results are extensively compared against the published data. It turns out that the current optimization approach can be very effective and robust in providing thermal optimal design of MCMs with a minimal total chip junction temperature through optimal chip placement     

基于正交试验的金丝键合工艺参数优化

金丝键合是实现微波多芯片组件电气互连的关键技术。介绍了引线键合技术的基本形式,分析了键合工艺参数对键合质量的影响。基于正交试验方法,通过对影响25μm金丝键合第一键合点质量的工艺参数优化进行试验研究,确定最优化的工艺参数水平组合,达到提高金丝键合工艺可靠性的目的。     

确好芯片商业化的关键问题

基于老化筛选技术的确好芯片KGD是现行多芯片封装结构中的关键芯片,具有封装成本低、可靠性高、体积小、易封装集成等优点,其应用前景广泛,如多芯片组件、多芯片封装、系统封装、功率系统封装、微系统封装、堆叠封装、混合集成电路等。文章对KGD技术做了分类总结,综述了近几年KGD技术的研发进展,指出KGD进一步发展的商业化关键问题。     

Synthesis of thermal RC-networks for system-in-packages

The applicability of system-in-package (SiP) type structures may be limited due to chip-to-chip thermal interactions. Therefore all significant heat sources have to be considered in the design to ensure safe operating temperatures. In this paper, we propose a generic compact thermal model (CTM) synthesis method for multichip packages that takes dynamic chip-to-chip interactions and different boundary conditions into account. The method is demonstrated with a stacked three-dimensional multichip module. Dynamic thermal characteristics of the module are studied by means of detailed finite element simulations and the results are considered as reference data in the synthesis. The CTM is optimized to diverse conditions typical to the application-specific environment, and the accuracy of the model is found sufficient for thermal design purposes.     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.     

High-yield assembly of multichip modules through known-good IC'sand effective test strategies

Multichip module technology has been shown to offer significant improvements for electronics equipment in the areas of miniaturized size, reduced weight, capability for higher frequency operation, improved thermal performance, and improved reliability. Production applications for multichip modules (MCMs) have grown from high-end computer and aerospace modules to include such diverse products as telecommunications, automotive, and consumer electronics modules. One of the keys to economic success in all applications is the achievement of high manufacturing yields. Yield losses must be kept very low compared with module costs in order to remain economically competitive. Two parameters with a very strong impact on manufacturing yield, known-good components entering assembly and test strategies at various levels of assembly, are discussed. Current industry practice is surveyed and recent progress on MCM infrastructure development is summarized     

Multidisciplinary Placement Optimization of Heat Generating Electronic Components on a Printed Circuit Board in an Enclosure

A multidisciplinary placement optimization methodology for heat generating electronic components on a printed circuit board (PCB) subjected to forced convection in an enclosure is presented. In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed. The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods. Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat source at an arbitrary location on the board, while temperature rise due to multiple heat sources is calculated using a superposition method. Compact thermal models are used for the electronic components thermal modeling. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate its capabilities, the present methodology is applied to a test case involving multiple heat generating component placement optimization on a PCB.     

基于热叠加模型的叠层3D多芯片组件芯片热布局优化研究

 叠层三维多芯片组件(3D Multi-Chip Module,MCM)芯片的位置布局直接影响其内部温度场分布,进而影响其可靠性.本文研究了叠层3D-MCM内芯片热布局优化问题,目标是降低芯片最高温度、平均芯片温度场.基于热叠加模型并结合热传导公式,选取芯片的温度作为评价指标,确定出用于3D-MCM热布局优化的适应度函数,采用遗传算法对芯片热布局进行优化,得出了最优芯片热布局方案,总结出了可用于指导叠层3D-MCM芯片热布局设计的热布局规则;采用有限元仿真方法,对所得的热布局优化结果进行验证,结果表明热布局优化结果与仿真实验结果一致,本文所提出的基于热叠加模型的MCM热布局优化算法可实现叠层3D-MCM芯片的热布局优化.     

Experimental validation of a thermal modelling method dedicated to multichip power modules in operating conditions

In this paper, we present an implementation of a thermal modelling method applied to a multichip module used as a power converter. Analytical functions of thermal impedances, with original formulations for the mutuals are defined. They are derived from 3D thermal simulations and experimental validations with direct chips temperature measurements. Finally, simulations are performed in order to improve the capability of our model to assess, with fast computation, the thermal constraints applied on the multichip module in a real operating condition.     

A hybrid optimization approach for chip placement of multi-chip module packaging

The aim of this article is to provide a systematic method to perform optimization design for chip placement of multi-chip module in electronic packaging. Based on the investigation of the structural and thermal characteristics of multi-chip module, the key performance indexes of multi-chip module that include the lowest internal temperature objective, thermal-transfer accuracy, chip placement are analyzed. A hybrid model is presented by using genetic algorithm and response surface methodology for optimization. Furthermore, some design processes for improving the performance are induced. Finally, an example is discussed to apply the method.     

多芯片组件散热的三维有限元分析

基于有限元法的数值模拟技术是多芯片组件(Multichip Module)热设计的重要工具。采用有限元软件ANSYS建立了一种用于某种特殊场合的MCM的三维热模型,对空气自然对流情况下,MCM模型的温度分布和散热状况进行了模拟计算。并定量分析了空气强迫对流和热沉两种热增强手段对MCM模型温度分布和散热状况的影响。研究结果为MCM的热设计提供了重要的理论依据。     

Testing multichip modules

Too complex to be tested as a chip and too packaged to be probed like a board, the multichip module presents a new set of challenges to the test engineer. The author describes how, until dedicated testers are developed, applying board-type tests using an IC tester will prove to be the most effective test methodology