A fully integrated 0.13-/spl mu/m CMOS mixed-signal SoC for DVD player applications

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G/sub m/-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10/sup -6/ of bit-error rate (BER) is obtained for the focus offset margins over /spl plusmn/0.5 /spl mu/m. This SoC is fabricated in 0.13-/spl mu/m one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm/sup 2/ die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

Line and receiver interface circuit for high-speed voice-band modems

A single-chip implementation of the analog signal processing functions required for full-duplex voice-band modem operation over twisted pair wires is described. Echo path signal-to-signal harmonic distortion plus noise exceeds 65 dB. The device is implemented in a 3.5-/spl mu/m twin-tub CMOS process, and typically dissipates 180 mW.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.     

Laser link cutting for memory chip repair

Link processing with individual laser pulses has become an industry standard process in IC memory chip manufacturing. It is gaining wide acceptance in analog chip reprogramming and tuning as well. Traditional laser processing, using the standard output of Nd:YAG at 1.064-/spl mu/m and Nd:YLF at 1.047-/spl mu/m laser wavelengths, works well for polysilicon links but is not satisfactory for metal links. This paper describes the physics modeling and computer simulation of the laser link process and a new technique of using 1.3-/spl mu/m laser wavelength for the process. While light absorption of link materials at 1.064-, 1.047-, and 1.3-/spl mu/m wavelengths are relatively the same, the absorption of a Si substrate at 1.3 /spl mu/m is considerably less. The improved absorption contrast between the link material and silicon substrate at 1.3-/spl mu/m delivers a much wider laser process window. Both simulation and experimental results are given and discussed. A brief introduction of another new technique, which uses UV laser pulses for link processing, is given. This UV laser process delivers a laser beam spot size much smaller than 1.5 /spl mu/m.     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

A mixed-mode polynomial cellular array processor hardware realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heun's iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.     

An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications

This paper describes an ultralow-power switched opamp-based integrated analog-to-digital converter (ADC) for cardiac pacemakers applications. The ADC consumption, measured on 10 chip samples and averaged, is 8.18 /spl mu/W (stand-by value: 1 nW) for the analog part and of 9.71 /spl mu/W (5 nW) for the digital one, using a supply battery of 2.8 V. The converter has a resolution of 10-b, its typical operating clock frequency is 32 KHz (2.9 KS/s sampling rate) and is able to reach the same resolution at 2 V (0.7 KS/s sampling rate), with a dissipation of 1 /spl mu/W and 1.3 /spl mu/W for analog and digital part, respectively.     

A true-1-V 300-/spl mu/W CMOS-subthreshold log-domain hearing-aid-on-chip

This paper presents a true very low-voltage low-power complete analog hearing-aid system-on-chip as a demonstrator of novel analog CMOS circuit techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-/spl mu/A application specific integrated circuit integrating a complete hearing aid in a standard 1.2-/spl mu/m CMOS technology is presented along with exhaustive experimental data. To the authors' knowledge, the presented system is the only CMOS hearing aid with true internal operation at the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

A fully integrated analog front-end macro for cable modemapplications in 0.18-μm CMOS

An analog front-end (AFE) module designed for use together with a digital cable modem transceiver on one single die is presented. All the analog functionality is implemented in a pure 0.18-μm CMOS process with 1.8-V supply. Besides the critical requirements toward substrate and supply isolation, the design of the high-order antialiasing filter, the high-performance analog-to-digital converter, and the low-jitter phase-locked loop are most challenging. With a silicon area of 9.9 mm ² and a power dissipation of less than 1 W, this 3-channel AFE can be considered a reference design for first-IF sampling (surface acoustic wave (SAW)-less) cable modem systems     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

Analog CMOS circuit design and characterization for optical coherence tomography signal processing

We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 /spl mu/m low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 1.2 V 12 b 60 MS/s CMOS Analog Front‐End for Image Signal Processing Applications

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front‐end (AFE) employing low‐power and flexible design techniques for image signal processing. An op‐amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog‐to‐digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 µm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal‐to‐noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm² and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.     

High-efficiency 1.3 /spl mu/m InAsP-GaInP MQW electroabsorption waveguide modulators for microwave fiber-optic links

High-efficiency electroabsorption waveguide modulators have been designed and fabricated using strain-compensated InAsP-GaInP multiple quantum wells at 1.32-/spl mu/m wavelength. A typical 200-/spl mu/m-long modulator exhibits a fiber-to-fiber optical insertion loss of 9 dB and an optical saturation intensity larger than 10 mW. The 3-dB electrical bandwidth is in excess of 20 GHz with a 50-/spl Omega/ load termination. When used in an analog microwave fiber-optic link without amplification, a RF link efficiency as high as -38 dB is achieved at 10 mW input optical carrier power. These analog link characteristics are the first reported using MQW electroabsorption waveguide modulators at 1.32 /spl mu/m.