InGaAs（InAIAs）／InP和InP／InAIAs湿法选择腐蚀研究

介绍了两种选择腐蚀液对InGaAs（InAlAs）／InP和InP／InAlAs异质结构材料选择腐蚀的实验结果，重点介绍在InAlAs上面生长InP的湿法选择腐蚀，用HCl：H3PO4：CH3COOH系列腐蚀液，InP／InAlAs选择比大于300。InP／InAlAs湿法选择腐蚀的结果可以很好应用到OEIC芯片制作中，并取得了较好的器件及电路结果。     

全钝化高性能InAlAs/InGaAs/InP HFET

<正>《Electronics Letters》1992年第7期报道了全钝化高性能InAlAs/InGaAs/InP HFET的研制。由于亚微米栅InAlAs/InGaAs/InP HFET具有优良的直流和微波性能,业已受到极大关注。但现有器件仍存在若干问题,例如:I/V特性中的弯折现象、栅极截止电流较高以及漏源击穿电压较低等。本文介绍的全钝化工艺使上述问题得以解决。由于采用了具有表面耗尽     

用于InP基DHBT制备的GaAs0.51 Sb0.49湿法腐蚀研究

介绍了采用基于柠檬酸、硫酸和磷酸的腐蚀溶液对气态分子束外延生长的InP衬底上GaAs0.51 Sb0.49湿法腐蚀研究工作.对不同体积比的腐蚀溶液的腐蚀速率和表面粗糙度进行了研究.和硫酸及磷酸基腐蚀液相比,柠檬酸/双氧水腐蚀液的腐蚀速率较慢但具有很好的表面粗糙度.作为验征,采用最优体积比5∶1的柠檬酸/双氧水腐蚀溶液,...     

在3英寸的InP衬底上使用光化学选择性干法凹槽腐蚀高平整度的N-InAlAs/InGaAs HEMT

我们已经开发了应用于InAlAs/InGaAs异质结构的大面积光化学选择性干法腐蚀.其中,使用CH_3Br气体和一个低压汞灯.InGaAs层的腐蚀速率是17nm/min,而InGaAs对InAlAs的腐蚀比大约是25∶1,用于N-InAlAs/InGaAs HEMT'S的干法凹槽是在3英寸表面使用光化学腐蚀形成的.当阈值电压是-0.95V时,整个表面的阈值电压标准偏差是18mv,对1.1μm长的栅可得到456ms/mm的跨导,而其标准偏差为14.9ms/mm。     

GaAs和InP基HFET工艺中的选择腐蚀技术

综合了 Ga As和 In P基 HFET工艺中的选择腐蚀技术的有关报道 ,重点介绍了应用 ICP设备和气体组合 BCl3+ SF6 进行异质结材料组合的干法腐蚀实验 ,腐蚀后在显微镜和扫描电镜下观察窗口平整干净、作迁移率测试等与湿法腐蚀的片子相比较没有看出差别 ,适宜用于器件工艺。     

InAs/GaSb二类超晶格材料湿法腐蚀工艺研究

研究了不同腐蚀溶液体系下铟砷镓锑(InAs/GaSb)二类超晶格材料的湿法腐蚀工艺。根据腐蚀效果选择了由柠檬酸(C6H8O7)、磷酸(H3PO4)、过氧化氢(H2O2)构成的混合腐蚀液。这种腐蚀液对InAs/GaSb材料腐蚀速率稳定,腐蚀后表面光滑,且下切效应小。同时,研究了该成分腐蚀液不同腐蚀液温度、浓度和各成分配比等条件对InAs/GaSb材料腐蚀速率,形貌和钻蚀情况的影响。根据实验结果配制了体积比为1∶1∶1∶40的柠檬酸(50%):磷酸(85%):过氧化氢(31%):水的腐蚀溶液,室温(20 ℃)下腐蚀速率约为9.48 nm/s。     

InAlAs/InGaAs/InP HEMT欧姆接触研究

应用Au/Ge/Ni系金属在InAlAs/InGaAs/InP HEMT上成功制作了良好的合金欧姆接触。采用WN和Ti双扩散阻挡层工艺优化欧姆接触,在样品上获得了最低9.01×10-8Ω.cm2的比接触电阻,对应的欧姆接触电阻为0.029Ω.mm。同时,在模拟后续工艺环境的20min250°C热处理后,器件的欧姆接触性能无显著变化,表明其具有一定的温度稳定性。     

用MOVPE生长的InAlAs/InGaAs/InP异质结MODFET

<正>《Electronics Letters》1991年8月报道了用MOVPE方法生长的高性能InAlAs/InGaAs/InP异质结MODFET。由于这种结构的材料具有较高的室温电子迁移率和高的有效电子速度,所以,它在超高频响应和增益方面,优于以GaAs为衬底的异质结MODFET。     

GaAs MISFET制备中柠檬酸/双氧水溶液对GaAs/AlxGa1-xAs结构的选择湿法腐蚀

用α台阶仪和原子力显微镜(AFM)研究了不同体积比的柠檬酸(50%)/双氧水溶液对GaAs/AlxGa1-xAs系统的选择湿法腐蚀特性,对AlxGa1-xAs停止层的组分和腐蚀液体积比进行了优化.当腐蚀液体积比在1.5∶1到2∶1范围时获得了最好的选择腐蚀效果.在25℃.温度条件下,当腐蚀液体积比为1.5∶1时,对Al摩尔分数x为0.2、0.3和1的GaAs/AlxGa1-xAs系统腐蚀比分别为45、74和大于200,表面腐蚀形貌均匀平整.将这种选择腐蚀技术用于GaAsMISFET的栅槽工艺,获得了良好的阈值电压均匀性.     

InGaAs／InAlAs／InP异质结构场效应晶体管的选择湿法腐蚀

ＩｎＧａＡｓ／ＩｎＡｌＡｓ／ＩｎＰ异质结构场效应晶体管的选择湿法腐蚀ＳｅｌｅｃｔｉｖｅＷｅｔＥｔｃｈｉｎｇｆｏｒＩｎＧａＡｓ／ＩｎＡｌＡｓ／ＩｎＰＨｅｔｅｒｏｓｔｒｕｃｔｕｒｅＦｉｅｌｄ－ＥｆｆｅｃｔＴｒａｎｓｉｓｔｏｒｓＭ．Ｔｏｎｇ等１引言异质结构...     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively     

InGaAs/InAlAs HEMT with a strained InGaP Schottky contact layer

The authors have fabricated an InGaAs/InAlAs HEMT structure with a strained InGaP Schottky contact layer to achieve selective wet gate recess etching and to improve reliability for thermal stress. Strained In_0.75Ga_0.25P grown on InAlAs has been revealed to have sufficient Schottky barrier height for use as a gate contact. Threshold voltage standard deviation has been reduced to one fifth that of a conventional InGaAs/InAlAs HEMT, as a result of successful selective recess etching. After thermal treatment at 300°C for 5 min, the drain current and transconductance did not change, while those of the conventional HEMT decreased by more than 10%     

Heterojunction InAlAs/InP MESFETs grown by OMVPE

Lattice-matched InAlAs/n-InP and InAlAs/n⁺-InP heterostructure MESFETs with extrinsic transconductances of 220 and 155 mS/mm, respectively, have been fabricated on semi-insulating InP substrates. Maximum stable gains of 11.5 dB for the 1.25-μm-gate n-InP channel and 10 dB for the 1.0-μm-gate n⁺-InP channel devices were measured at 10 GHz. An extrapolated f_max of 42 GHz was obtained for the n⁺-channel MESFET     

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design     

InGaAs/InGaAlAs/InAlAs/InP SCH-MQW laser diodes grown by molecular-beam epitaxy

InGaAs/InGaAlAs/InAlAs/InP separate-confinement hetero-structure-multiquantum-well (SCH-MQW) laser diodes have been fabricated by molecular-beam epitaxy (MBE), and room-temperature pulsed operation at 1.57 ?m has been achieved. This SCH-MQW laser is composed of InGaAs well layers, InGaAlAs quaternary barrier layers, and InAlAs and InP cladding layers.     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

Admittance spectroscopy of ring diode InGaAs/InAlAs/InP quantum-well structures

The admittance of ring planar diode Au/InGaAs/InP and Au/InGaAs/InAlAs heteronanostructures on i-InP has been studied. The structures are constituted by a silicon ??-doped layer and an InGaAs quantum well (QW) in InP or InAlAs epitaxial layers. An analysis of the capacitance-voltage and conductance-voltage characteristics yielded distribution profiles of the electron concentration and mobility in the vicinity of the QW and ??-doped layer. It is shown that lowering the temperature leads to an increase in the electron concentration and mobility in the QW.     

Charge storage in InAlAs/InGaAs/InP floating gate heterostructures

Charge retention in floating gate InAlAs/InGaAs/InP field effect transistors is limited by lateral electron motion along the storage channel, a different direction for motion than found for AlAs/GaAs devices. Storage times as a function of temperature for the InP based alloy devices are reported and compared with similar AlAs/GaAs devices by using Poisson equation models.<>