φ300mm内存制造的新芯片检查策略

在晶圆制造的良率维持、缺陷的侦测与再检查,目前的检测方法,很难提供高侦测感度,与高取样率,全芯片扫描,快速产能,并维持低成本。传统的检测方法,分别以高感度的明视场检查,与高产能的暗视场检查,无法再满足缺陷检查需求,特别是在大量晶圆产出的环境。在此,由力晶半导体提出创新的缺陷检查策略,即整合明视野暗视野检查机台,并最佳化,以使产出最大化,异常缺陷反应快速化等目标。     

Extraction of wafer-level defect density distributions to improveyield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDD's per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis     

In-line yield prediction methodologies using patterned waferinspection information

Due to the advances in in-line inspection technology it is now possible to obtain an early in-line prediction of yield. This paper introduces and compares two new in-line yield prediction methodologies: (1) multilayer critical area method and (2) defect-type-size kill-ratio method. These methods are more accurate than the past and other current approaches used in the semiconductor industry. The first method uses the design layout information along with the in-line defect data, whereas the second method uses the defect and yield data to empirically derive the kill-ratios. We demonstrate our methodologies using data collected in a real wafer fabrication facility at the polysilicon gate (Poly), and the first and second interconnect (Metal 1 and Metal 2) post etch inspection layers. We compare our in-line predictions with the actual yield     

Yield challenges in wafer stacking technology

Wafer stacking technology offers a higher performance in a smaller size with a lower cost option for microelectronic industries. However, it suffers from a compound yield loss which becomes a key challenge and a limiting factor in this technology. A compound yield loss in wafer stacking has been analyzed and yield challenges have been presented. Assuming a random defect density per wafer and no yield fallout from stacking processes, the compound yield of a bonded wafer pair has been estimated with the most commonly used yield model. As a result, it is proposed that a die area reduction for wafer stacking is needed in order to offer a great yield advantage. Both wafer testing and wafer size are also proven to influence significantly a die yield in a bonded wafer pair.     

A neural-network approach for semiconductor wafer post-sawinginspection

Semiconductor wafer post-sawing requires full inspection to assure defect-free outgoing dies. A defect problem is usually identified through visual judgment by the aid of a scanning electron microscope. By this means, potential misjudgment may be introduced into the inspection process due to human fatigue. In addition, the full inspection process can incur significant personnel costs. This research proposed a neural-network approach for semiconductor wafer post-sawing inspection. Three types of neural networks: backpropagation, radial basis function network, and learning vector quantization, were proposed and tested. The inspection time by the proposed approach was less than one second per die, which is efficient enough for a practical application purpose. The pros and cons for the proposed methodology in comparison with two other inspection methods, visual inspection and feature extraction inspection, are discussed. Empirical results showed promise for the proposed approach to solve real-world applications. Finally, we proposed a neural-network-based automatic inspection system framework as future research opportunities     

Validation of yield models with CMOS/SOS test structures

A methodology assessed to implement wafer level reliability relies on the design of specific test structures which must be as similar as possible to functional circuits geometries and lay-outs. In a second step, electrical tests provide wafer level data to validate the use of the Poisson yield model which gives defect densities. It is found that chips from the central area of the wafer present randomly distributed defects whereas those from the periphery are governed by a more systematic distribution.     

Simulation of yield/cost learning curves with Y4

This paper describes a prototype of a discrete event simulator-Y4 (yield forecaster)-capable of simulating defect related yield loss and manufacturing cost as a function of time, for a multiproduct IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product, and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies     

METRO-3D: an efficient three-dimensional wafer inspection simulator for next-generation lithography

Wafer inspection schemes for next-generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of deep ultraviolet (DUV) wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning, or full-field schemes can be extremely costly; therefore, simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional (3-D) simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a 3-D simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. We will present simulation results from METRO-3D for various wafer inspection schemes, including high NA schemes, on NGL topographies with highly absorptive materials.     

Laser-induced fluorescence spectroscopy and imaging ofsemiconductor wafers

Fluorescence spectra of selected films used in microelectronic fabrication have been recorded. We have used a 0.125-m focal length spectrophotometer and a 400-line/mm grating resulting in 4.2-nm spectral resolution. The optical setup employs a laser at 364 nm for excitation and a dark-field collection configuration-a geometry that we routinely use for laser scanning for inspection purposes. A simple, though thorough, analysis and methodology for the removal of the system spectral response is presented. Results show that films used in microelectronic fabrication, in general, yield a broadband fluorescence spectrum under 364-nm excitation. Further, a scanning system that bases the image contrast on laser-induced fluorescence from the wafer surface is described and demonstrated. It is shown that this is a particularly useful inspection/review modality when the wafer is at poly/metal process level and the contaminant is a fall-on or residue of an organic material     

基于像素分布特性的IC晶片视觉检测方法

IC晶片制造过程存在多种致命缺陷,致使芯片失效,导致成品率下降.冗余物缺陷是影响IC晶片成品率下降的重要原因,主要造成电路短路错误.针对冗余物缺陷对版图的影响,提出了一种简单可行的缺陷视觉检测方法,以实现冗余物缺陷的识别及电路失效形式的确定.根据摄取的显微图像的图像特征,利用光线补偿技术及形态滤波方法消除干扰噪声,以提高图像质量,采用投影定理及基于像素分布特性的检测方法,实现电路短路形式或缺陷未导致电路失效的识别.     

Strategy and metrics for wafer handling automation in legacysemiconductor fab

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as well as overall fab goals and attitudes that are required to achieve full wafer handling automation. After considering several approaches to staged fab automation, we selected an approach which eliminated all manual handling within specific fab modules, completing the automation within one group of modules before embarking on another module set. In this way, we limited both the initial scope and cost of the project while preparing to leverage its initial successes. This paper summarizes the methodology and metrics found useful for preparing the fab for change, executing the change, and successfully managing the overall project     

Improved Defect and Fourier Transform Infrared Spectroscopy Analysis for Prediction of Yield for HgCdTe Multilayer Heterostructures

The ability to accurately predict HgCdTe focal plane array (FPA) performance using nondestructive, postgrowth wafer analysis is of great importance. These predictions, if accurate, reduce costs by screening the wafers prior to processing, and selecting only those wafers that are most likely to yield FPAs that meet program specifications. In this paper, we examine the use of a macrodefect inspection tool, the NSX 1255, from August Technology. This inspection tool has the ability to measure defects 0.5 μm and larger and store the location and size data to a file. We have then, through the use of custom written software, been able to analyze these data on a wafer by wafer basis. We have also incorporated the use of a thin film transmission matrix model to analyze room-temperature Fourier transform infrared spectroscopy (FTIR) transmission spectra. This technique, which is applied to the entire wafer surface, can be used to determine the individual layer thicknesses as well as their compositions. Then, using analytical expressions for bandgap, absorption, and index of refraction, we can predict responsivity and quantum efficiency. Through the use of these two inspection tools and our analysis software, we are able to overlay FPA die information and perform statistics on a die-per-die basis. This allows us to effectively “pass” or “fail” each FPA based on the program specifications. We are then able to set a minimum criterion for the number of FPAs that pass on any given wafer. That wafer is then sent off to processing if it meets this criterion. Furthermore, knowing why a wafer fails before it reaches processing allows for real time feedback to the epilayer growth process. This allows for run-to-run adjustments in order to keep as many wafers within specifications as possible and increases yield overall. (Received October 24, 2006; accepted Feburary 26, 2007)     

New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

This paper will start with a discussion of why probe yield (the number of good chips per silicon wafer) is so important to financial success in integrated circuit manufacturing. Actual data will be quoted and a numerical example shown. A simple model will be given to demonstrate the main factors influencing yield and the relationship between yield and reliability of the final product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement, thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and control, automatic defect classification and data mining techniques. A proposal is made to extend these tools to the improvement of reliability of products already in manufacturing by maintaining absolute chip identity throughout the entire wafer fabrication, packaging and final testing steps.     

Defect cluster analysis for wafer-scale integration

A methodology for characterizing spatial defect distributions is presented. A correlation function approach providing spatial information not measurable with classical methods such as yield-versus-area curves is described. This additional information includes the spatial extent of defect clustering, the strength of clustering, and uncertainty in clustering magnitude. The correlation function methods are applicable to experimentally determined defect maps or to simulation results based on different assumptions concerning the spatial distribution of defects. It is also shown that the approach is useful in predicting yield for redundant circuit configurations when experimental data pertaining to the spatial distribution of defects are available. This type of yield prediction capability is important for judging the feasibility of various redundancy implementations, including wafer scale integration     

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.     

Systematic defect improvement integration of dual damascene processes development on nano semiconductor fabrication

Process defects of semiconductor wafer nanotechnology manufacturing process can often impact product yields, depending on the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. Manufacturing process-induced defects prevention should begin with an assessment of the critical risks associated with the wafer fabrications. Systematic identification and classification approaches have been introduced to improve the process yield by defects sampling and images reviewing. This study presents comprehensive investigation of a process defects monitor and integration on semiconductor copper manufacturing process and technology, and module process integration of the problem of defects reduction on semiconductor manufacturing processes. Experiments on electrical devices were performed to identify the defect source and determine the mechanism of defect formation, and integrated manufacturing processes implemented to eliminate defect issues are also investigated.     

AQL、LTPD以及“零缺陷”三种抽样检验的比较

抽样检验按照检验值的属性可以划分为计量抽样检验和计数抽样检验,而计数抽样检验又包括一次、二次以及多次抽样方案。文章主要介绍了计数型抽样检验中一次抽样方案的基本概念、抽样原理、表征参数、OC函数、OC曲线以及抽样方案辨别力指标。在此基础上,重点介绍了AQL抽样、LDPT抽样以及"零缺陷"抽样三种抽样检验方法的基本构架和检验流程。通过对三种抽样检验方法的分析对比,零缺陷抽样凭借其抽样方法简便、抽样方案经济、质量理念先进的特点,已经逐渐成为现代企业质量检验管理的潮流所向。     

Intelligent Camera for Surface Defect Inspection

An intelligent camera for surface defect inspection is presented which can pre-process the surface image of a rolled strip and pick defective areas out at a spead of 1 600 meters per minute. The camera is made up of a high speed line CCD, a 60 Mb/s CCD digitizer with correlated double sampling function, and a field programmable gate array（FPGA）, which can quickly distinguish defective areas using a perceptron embedded in FPGA thus the data to be further processed would dramatically be reduced. Some experiments show that the camera can meet high producing speed, and reduce cost and complexity of automation surface inspection systems.     

硅片Map图信息的提取和利用

分析了硅片Ｍａｐ图所提供的生产成品率和各类不合格芯片的位置分布信息，讨论了利用硅片之间Ｏｖｅｒｌａｐ法（重叠法）和硅片上Ｗｉｎｄｏｗ法（窗口法）对Ｍａｐ图进行的统计。着重讨论了：按硅片中不合格芯片密度的显著差异划分边缘区及中心区；不合格芯片局部聚集现象的定量表示；随机性强的不合格芯片的统计分布；有关信息由相应Ｃ语言软件自动提取，与Ｍａｐ图计算机测试进行联用，可用于生产监控、影响成品率因素分析和工艺缺陷的深入研究。     

An Alternative Integrated-Circuit Yield Model

This paper develops a model to predict the number of good integrated circuits (the yield) from a semiconductor wafer processing line. The model is different from other published models and predicts observed outcomes better. Many models tend to predict lower yields than those actually achieved because those models are inherently incapable of predicting the average number of good chips per wafer. The model developed in this paper is based on combinatorial analysis and considers the number of die sites on the wafer and the total number of yield detracting defects on the wafer. In contrast the other models referenced require at least two parameters as input data: the area of one die site or chip and the average defect density. A third parameter, the Cdf of the defect density is often implied by the selection of the model.