A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

A 900-Mb/s CMOS data recovery DLL using half-frequency clock

A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm². It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW     

Microwave properties of silicon junction tunnel diodes grown bymolecular beam epitaxy

The bias dependence of the single-port microwave reflection gain of 15 μm-diameter Si Esaki tunnel diodes, grown by molecular beam epitaxy, was studied as a function of frequency. A simple equivalent circuit accurately modeled the data and yielded the forward-bias junction capacitance, which cannot be obtained by conventional low frequency capacitance-voltage techniques. The diodes were highly-doped step p-i-n junctions and exhibited a peak current density of 16 kA/cm ². The microwave reflection gain and cut-off frequency were 12 dB land 1.6 GHz, respectively, with a speed index (slew rate) of 7.1 V/ns     

High-speed QPSK modulator and demodulator with subharmonic pumping

The authors describe a subharmonically pumped QPSK modulator and demodulator using pairs of beam-leaded Schottky diodes and appropriate high-pass and low-pass filters on dielectric substrates. A modulator and a demodulator were operated in cascade at a carrier frequency of 13 GHz with a common pump at 6.5 GHz. This circuit showed clean eye diagrams of the recovered data trains up to 1.5 Gb/s with corresponding error rates of less than 10^-11. The circuits can be readily scaled to higher frequencies with a proportional increase of the information rate     

A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mum CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 2³¹-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10^-12 are 300 and 10 mV_pp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68times0.8 mm² where the active circuit area only occupies 0.32times0.6 mm²     

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 2⁷ - 1 calibration improved the measured bit error rate from 4.6 x 10^-2 to less than 10^-13.     

Performance of a flux locked series SQUID array

The operation of a SQUID array with 100 DC SQUIDs has been demonstrated using a single flux-locked loop. The SQUID array had a maximum dynamic range of ±1.3×10⁸/√(Hz) in the low frequency region, a high slewing rate over a wide frequency range, and an extrinsic white noise energy sensitivity of 6×10^-31J/Hz. These data were obtained with a very simple feedback circuit made from three inexpensive operational amplifiers that operated in the DC-feedback mode. The feedback loop did not have any impedance matching circuit between the SQUID array and the room temperature electronics. Our results show that a SQUID array can have a significant impact on those applications that demand good noise performance and a very high dynamic range     

An experimental large-capacity semiconductor file memory using16-levels/cell storage

A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3-μm CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 μs, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10^-7 h^-1)     

0.5-25 GHz inductorless single-ended resistive mixer in 0.13 μm CMOS

A wideband inductorless resistive down-conversion mixer in 0.13 μm CMOS technology is presented. The mixer provides a conversion loss of 9?11.7 dB over a frequency range of 0.5?25 GHz at LO power of 6 dBm. The circuit exhibits an input-referred 1 dB compression point and IIP3 of 4.7 and 11.5 dBm, respectively. The mixer consumes only 0.2 mA from 1.5 V for biasing. The isolation between the ports is higher than 10 dB for the whole frequency range. The circuit is realised without inductors, thus offering very wide bandwidth. The chip size including the pads is 0.23 mm², and the circuit active area is only 0.014 mm².     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

2-4 GHz monolithic lateral p-i-n photodetector and MESFET amplifieron GaAs-on-Si

The design, fabrication, and evaluation of broadband lateral p-i-n photodetectors monolithically integrated with multistage MESFET amplifiers on GaAs-on-Si are described. Unique features of this approach are that (a) the lateral p-i-n structure is compatible with monolithic microwave integrated circuit (MMIC) technology and (b) the p-i-n detector is fabricated directly on the GaAs buffer layer without p⁺ and n⁺ implants, thus resulting in a simplified fabrication process. The operation of the circuit is compared to that of a similar circuit fabricated on a GaAs substrate. A quantum efficiency exceeding 60% has been measured for the p-i-n detectors. The 2- to 4-GHz frequency responses of one- and two-stage p-i-n/FET preamplifiers are presented. The response varies ±3 dB over the frequency band     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Theoretical study of a Gunn diode in a resonant circuit

A computer simulation of a GaAs Gunn diode in a parallel resonant circuit has been made to determine the optimum device and circuit parameters. The maximum dc to RF efficiency, 5 to 8 percent, is obtained when the product of doping and length is between 10¹²and 2 × 10¹²cm^-2, the product of frequency and length is 10⁷cm/s, and the bias voltage divided by length is 8000 V/cm for a load resistance of30 R_{0}where R0is the low-voltage resistance of the diode. The product of output power and load resistance varies with frequencyfasC f^{2}whereCis 12,000 watt-ohm-GHz²for a load resistance of50 R_{0}. The frequency can be varied over an octave tuning range by the resonant circuit.     

An experimental Josephson digital correlator

A circuit capable of performing correlation of two sets of 16-sample, one-bit digital data has been designed and tested up to a clock frequency of 12 GHz. The correlator consists of two 16-b shift registers for delay and storage elements and an array of 16 exclusive-OR gates for the multiply-and-add function. It is fabricated using an Nb/AlO_x/Nb Josephson-junction process at a critical-current density of 1000 A/cm²     

A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz     

高稳双层恒温晶振的设计

为了提高晶体振荡器的温频特性,设计了双层恒温高稳定度晶体振荡器。振荡器温控系统采用双层控温结构,通过多点加热和多点感温的方式,改进了恒温槽的设计,极大地改善了产品的频率温度稳定度。同时电路采用SC切晶体谐振器和Colpitts电容三点式振荡电路,提高了产品的短期频率稳定度。通过实际测试,该振荡器温度-频率特性和短期频率稳定度分别达到<±2E ^-10(-30~+70 ℃)和<1E ^-12/s的指标,均比同类产品提高1个量级以上,同时其老化率指标可达<5E ^-11/日。     

Electrical Backplane Equalization Using Programmable Analog Zeros and Folded Active Inductors

In this paper, we present a low-power small-area electrical backplane equalizer using programmable analog zeros and folded active inductors. We also present a dc-offset cancellation circuit, which occupies less chip area than the traditional offset cancellation schemes. The equalizer circuit was fabricated in a 1.0-V 90-nm CMOS process. With one zero stage, the equalizer occupies 0.015-mm² chip area and dissipates 12 mW of power. At 4.25-Gb/s data rate, the equalizer provides 7.8-dB gain boost at the Nyquist frequency. Without the use of any transmitter equalization, the analog zero equalizer demonstrated error-free transmission for pseudorandom-bit-sequence-31 data patterns over 34-in lossy FR4 backplanes.     

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm². The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2⁷-1 PRBS. The measured bit error rate for a 10 Gb/s 2⁷-1PRBS is less than 10^-12.     

Micromechanical accelerometer integrated with MOS detection circuitry

A cantilever beam accelerometer is described in which the small cantilever sensing element is integrated with and fabricated alongside MOS detection circuitry. The total area of the detector/circuit combination is about 15000 µm²(24 mil²). Fully compatible and conventional materials and processing steps are employed throughout the fabrication schedule. Accelerations of the chip normal to its surface induce motions in the cantilever beam. These motions result in capacitance variations which drive the simple MOS detection circuit. Sensitivities of about 2.2 mV/g of acceleration were measured, corresponding to beam motions of about 68 nm/g, with a beam mechanical resonant frequency of 2.2 kHz. These results were in close agreement with detailed mechanical calculations and circuit modeling.     

A Novel BPSK Demodulator for Biological Implants

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector based phase-locked loop allowing for robust performance compared to prior art. Two different circuit implementations for the novel demodulator architecture are proposed. Based on theoretical analysis, the maximum data rate of the demodulator is derived to be 1/8th of the carrier frequency. For experimental validation, a prototype was implemented for a 13.56-MHz BPSK demodulator in a 0.5-$mu{hbox {m}}$ CMOS technology. The circuit occupies 1 ${hbox {mm}}^{2}$ chip area and consumes 3-mW power without any circuit optimization and can be further improved. Bit-error rate measurements have also been presented for a 20-kbs data rate.