Resistive Bridging Defect Detection in Bulk,FDSOI and FinFET Technologies

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.     

PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

Soft defect localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across the device under test (DUT). This technique has proven its usefulness for quickly locating defects that are temperature, frequency, and/or voltage dependant, for example, scan logic soft fault. However, due to high sensibility at analogue circuits SDL meets great challenges. This work gives a new flow to analyze soft functional failure in advanced logic products using fault based analogue simulation and SDL. The paper will present one case study illustrating the application of analogue simulation based soft defect localization flow as an effective means to achieve fault isolation.     

Metal defect localization of GaAs or Si based ICs by dynamic emission microscopy

Metal defect has become one of the major failure mechanisms of integrated circuit, whose localization might need skillful techniques in failure analysis, especially within function issues. Popular failure analysis method has been suggested for about two decades, such as PEM and laser stimulation microscopy. Most of the reported works are based on CMOS silicon substrate ICs, and mostly for frontside analysis by dynamic method. Since Gallium Arsenide (GaAs) based integrated circuit is developing very fast, the failures are also bringing challenges. Conventional dynamic method should be implemented in accordance with GaAs features.Emission characteristics of GaAs based pseudomorphic HEMT (PHEMT) and silicon based ICs were discussed in this paper corresponding to some possible consequences caused by metal defect. We proposed a dynamic emission microscopy method to solve the GaAs based high speed digital circuit open failure consist of DCFL inverters and performed a backside analysis on silicon based flipchip IC with metal bridge defect.     

Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits

We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a transistor-replication method based on coding theory. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by: 1) modeling each circuit's ability to tolerate defects and 2) calculating the cost of the defect tolerance as each circuit's redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a function giving the failure probability of the entire demultiplexer circuit as a function of the defect probabilities of its component transistors, for both defect types. With the advent of defect tolerance as a new design goal for the circuit designer, this new form of performance analysis has become necessary.     

Intra-Cell Defects Diagnosis

The diagnosis is the process of isolating possible sources of observed failures in a defective circuit. Today, manufacturing defects appear not only in the cell interconnection, but also inside the cell itself (intra-cell defect). State of the art diagnosis approaches can identify the defect location at gate level (i.e., one or more standard cells and/or inter-connections can be provided as possible defect location). Some approaches have been developed to target the intra-cell defects. In this paper, we propose an intra-cell diagnosis method based on the “Effect-Cause” paradigm aiming at locating the root cause of the observed failures inside a logic cell. It is based on the Critical Path Tracing (CPT) here applied at transistor level. The main characteristic of our approach is that it exploits the analysis of the faulty behavior induced by the actual defect. In other word, we locate the defect by simply analyzing the effect induced by the defect itself. The advantage is the fact that we are defect independent (i.e., we do not have to explicitly consider the type and the size of the defect). Moreover, since the complexity of a single cell in terms of transistor number is low, the proposed intra-cell diagnosis approach requires a negligible computational time. The efficiency of the proposed approach has been evaluated by means of experimental results carried out on both simulations-based and industrial silicon data case studies.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.     

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer

This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer. Simulation results demonstrate that bridging fault effects of the synchronizer depend on fault location, bridging resistance value, the input signal (rising and falling), and the time of input signal application. The issues of bridging fault behavior under the consideration of process variation, and the relationship between bridging faults and the synchronizer failure mechanisms are also discussed.     

Fault tolerant system based on IDDQ testing

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.     

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.     

The device characteristics of missing LDD implantation via nanoprobing techniques for localized failure analysis

In the recent years, localization of subtle defects has required device electrical data. Nanoprobing systems based on scanning electron microscopy (SEM) or atomic force microscopy (AFM) have become a significant tool for device measurement in failure analysis (FA) Labs. Failure Analysts can use electrical characteristics to isolate failure location in the metal–oxide–semiconductor field-effect-transistor (MOSFET). The missing lightly doped drain (LDD) implant is an example of a critical failure mechanism for the MOSFET and cell in the SRAM which is localized using nanoprobing. In this article, device data analysis and theoretical deductions are discussed related to missing LDD doping. Device data is used to propose a full set of characteristic for missing LDD. The simulation from a mature tool is able to support the electrical characteristics. The capability and challenge of the following physical FA to reveal the defect are also discussed.     

Patterning approach for detecting defect in device manufacturing

Compact handheld devices which were a dream in the past are now a reality; this has been enabled by miniaturization of circuit architectures including power devices. Scaling down of the design feature sizes does come with a price with an increase in systematic defects during chip manufacturing. There are generally two methods of inline defect detection adopted to monitor the semiconductor device fabrication—optical inspection and electron beam inspection. The optical inspection uses ultra-violet and deep ultra-violet (UV/DUV) light to find patterning defects on the wafer. While the electron-beam inspection uses electron charge and discharge measurement to find electrical connection defects, both are a costly procedure in terms of resources and time. The physical limit of feature resolution of the optical source is now making the defect inspection job difficult in miniaturized application specific integrated circuit (ASIC). This study is designed to test the patterning optimization approach on both inspection platforms. Using hotspot analysis weak locations are identified in the full chip design, and then they are verified in the inline wafer inspection. The criterion for hot-spot determination is also discussed in this paper.     

基于SEM电压衬度的缺陷定位方法研究

光发射显微分析、光致电阻变化技术两种电失效定位方法在精确定位缺陷上存在局限性,为此提出了基于SEM电压衬度的联用方法用于精确定位集成电路缺陷。首先根据电特性测试进行光发射显微分析或者光致电阻变化分析,结合电路原理和版图,提出失效区域的假设,再进行电压衬度像分析,通过衬度翻转可精确和快速确定缺陷位置,最后通过FIB或者TEM对缺陷进行表征。案例研究显示,有源电压衬度可定位双极型电路铝金属化开路失效,无源电压衬度定位CMOS电路多晶硅栅刻蚀异常引起的漏电流失效,结合形貌和材料分析得出缺陷形成机理和根本原因。     

Defect analysis and yield degradation of integrated circuits

Various attempts have been made to analyze the yield of integrated circuits in the presence of point defects. This paper analyzes the yield considering both radial and angular variation in the defect density. The effect of statistical variations in the average defect density from slice to slice is also included. Different types of defects which affect the yield are reviewed. The degradation in yield due to point defects, line defects, area defects, and defect clusters is considered in detail. A method of optimum chip placement is described, and the results of computer calculations showing yield as a function of chip size are given assuming different defect density distributions. The results are primarily applicable to large integrated circuit chips.     

Temperature Characteristics of BJMOSFET

The resolution expression for the temperature dependence of the current and threshold voltage is deduced as well as the analysis of temperature characteristics of BJMOSFET. Equivalent circuit of analysis and simulation has been established for the BJMOSFET temperature characteristics. By using the general circuit simulation software of PSpice9 and computer simulation, characteristic graphs of the BJMOSFET output characteristic, transient characteristic and amplitude-frequency characteristic with temperature variation are obtained. The results accorded very good with theoretical analysis and proved that BJMOSFET has better temperature characteristics than traditional MOSFET.     

The combinational or selective usage of the laser SQUID microscope,the non-bias laser terahertz emission microscope,and fault simulations in non-electrical-contact fault localization

Recently, in the field of fault localization of LSI chips, several non-electrical contact techniques have been proposed. The techniques include the laser SQUID microscope (L-SQ) and the non-bias laser terahertz emission microscope (NB-LTEM). Both techniques have pros and cons. The L-SQ, for examples, can localize open defects in some cases, but it requires closed circuit. The NB-LTEM can localize open defects and short defects, and not requires closed circuit. The NB-LTEM, however, cannot localize open defects in some cases. The fault simulation specially designed for the L-SQ or the NB-LTEM makes it precise or efficient to localize defects. The combinational or selective usage of the L-SQ, the NB-LTEM and the related simulations makes it possible to localize defects in many cases. In this paper, we would like to review our results and organize them from the viewpoint of failure mode and defect sites.     

Delay caused by resistive opens in interconnecting lines

An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.     

Decision-Level Defect Prediction Based on Double Focuses

This research mainly expounds upon the decision-level software defect prediction theory. The defect characteristics is the first research focus. For the first re-search focus, a characteristic comparison set is built out of the existing defect characteristics according to the dissim-ilarity of defect characteristics and the defect character-istics are organized outside the characteristic comparison set into some defect characteristic clusters to reduce the scale of the characteristic data. The defects is the second research focus. For the second research focus, the vector weights are assigned to the defect characteristics contained in the defects according to the minimum critical character-istic set. Moreover, the multi-agent algorithm integration technology is used to predict defects according to the re-pulsive relationship between similar defect clusters.     

基于探针法的FED电极缺陷检测系统设计

针对FED显示屏电极的特征,提出一种FED电极缺陷检测系统,用于检测FED电极的短路和断路等缺陷。系统分为硬件和软件两部分,硬件部分由CCD摄像头初始定位和对准模块、单片机数据测试和传输模块、计算机数据接收和处理模块组成;软件部分包括单片机预处理部分的底层程序设计和计算机部分面向对象的高级程序设计。经过硬件设计安装和软件编程调试,该FED电极缺陷检测系统已经在实验中得到应用。     

基于X射线焊缝图像缺陷特征提取的研究

本文针对X射线焊缝图像的复杂性,提出了准确快速的提取焊缝区域和缺陷的方法。由于检测到的X射线图像具有对比度不高、光照不均、缺陷边缘模糊、图像噪声多、存在较大的背景起伏等缺点,首先对含有缺陷的焊缝图像进行一系列的图像预处理;然后采用自适应阈值分割算法来提取焊缝缺陷区域,为缺陷特征测量做准备工作;最后,在图像本身所包含的几何特征、灰度特征、结构信息、颜色信息等特征中,对缺陷图像进行几何特征的测量,以便对缺陷类型进行分类。结果表明,该方法能较准确地提取射线图像的焊接缺陷,并能较准确的获取该缺陷的几何和代数特征,具有良好的适应性和实用性。     

Effects of the compositional ratio distribution with sulfurization temperatures in the absorber layer on the defect and surface electrical characteristics of Cu2ZnSnS4 solar cells

Although Cu₂ZnSnS₄ (CZTS) has attracted attention as an alternative absorber material to replace CuInGaSe₂ (CIGS) in solar cells, the current level of understanding of its characteristic loss mechanisms is not sufficient for achieving high power conversion efficiency. In this study, which aimed to minimize the characteristic losses across the devices, we examined the relations between the compositional ratio distribution in the absorber layer, subsequent defect formation, and surface electrical characteristics. A high‐temperature sulfurization process was used to improve the crystallinity of the absorber layer, which increased the uniformity of the compositional ratio distribution and consequently suppressed the formation of a ZnS secondary phase on the CZTS/MoS₂ interface. Because defects and defect clusters generated in the absorber layer are shallower when the compositional ratio distribution is uniform, the electron‐hole recombination loss is reduced. These characteristics were confirmed by measuring the defect energy level using admittance spectroscopy and by analyzing the surface potential and current characteristics. These measurements revealed that improving the compositional ratio distribution suppresses the formation of deep‐level defects and reduces the rate of carrier recombination. In addition, improving the compositional ratio distribution substantially contributes to improving the series resistance and short circuit current density characteristics. Copyright © 2015 John Wiley & Sons, Ltd.