Modified Face-Down Bonding of Ridge-Waveguide Lasers Using Hard Solder

A modified face-down bonding technique of ridge-waveguide laser diodes (LDs) using 80Au20Sn solder has been performed. For ease of manufacturability, a bonding window with good bonding integrity and improved optical performance was determined. Metallographical investigation showed that the solder joint comprised of a layer of delta phase compound near the solder/heatsink interface, a layer of (Au,Ni)Sn intermetallic compound (IMC) at the solder/heatsink interface, and zeta' phase Au/Sn compound at the center of the solder joint. The delta phase shifted to the interfaces after reflow was postulated by its lower surface tension than zeta' phase Au/Sn compound. Good bonding integrity was observed with LD residues still adhering onto the bond pad after die shear testing. Scanning electron microscopy (SEM)/energy dispersive X-ray (EDX) analyses of the fracture surface showed that the fracture occurred within the LD, at the GaAs/SiN interface. LDs bonded with this modified bonding process achieved an optical improvement of 2.5-3X compared to the unbonded LDs due to its good thermal management. These bonded LDs further exhibited good long-term reliability with no significant degradation in optical performance and no significant microstructure evolution in the solder joint after 500 thermal cycling test.     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

Effect of microstructure of Au80Sn20 solder on the thermal resistance TO56 packaged GaN-based laser diodes

Au80Sn20 alloy is a widely used solder for laser diode packaging. In this paper, the thermal resistance of GaN-based blue laser diodes packaged in TO56 cans were measured by the forward voltage method. The microstructures of Au80Sn20 solder were then investigated to understand the reason for the difference in thermal resistance. It was found that the microstructure with a higher content of Au-rich phase in the center of the solder and a lower content of (Au,Ni)Sn phase at the interface of the solder/heat sink resulted in lower thermal resistance. This is attributed to the lower thermal resistance of Au-rich phase and higher thermal resistance of (Au,Ni)Sn phase.     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

Microstructure of eutectic 80Au/20Sn solder joint in laser diode package

Laser diodes (LD) are usually bonded onto heat sinks for the purposes of heat dissipation, mechanical support and electrical interconnect. In this study, energy dispersive X-ray analysis (EDX) and electron backscatter diffraction (EBSD) are employed to investigate the microstructure evolution of 80Au/20Sn solder joint in LD package. During reflow, Pt-Sn and (Au, Ni)Sn IMCs were formed at the respective LD/solder and solder/heatsink interfaces, while δ, β and ζ′ phases of Au/Sn intermetallics were found in the solder joint. The Au-rich β and ζ′ phases in the solder joint limit the growth of interfacial IMCs. Chip shear testing showed that the failure occurred within the LD, with partial brittle fracture at the GaAs substrate and partial interfacial delamination at the GaAs/SiN interface. The strong solder bond can be attributed to the high mechanical strength of 80Au/20Sn solder, which provides improved stability for high temperature applications.     

Microstructure evolution of gold-tin eutectic solder on Cu and Ni substrates

The microstructures of the eutectic Au20Sn (wt.%) solder that developed on the Cu and Ni substrates were studied. The Sn/Au/Ni sandwich structure (2.5/3.75/2 μm) and the Sn/Au/Ni sandwich structure (1.83/2.74/5.8 μm) were deposited on Si wafers first. The overall composition of the Au and the Sn layers in these sandwich structures corresponded to the Au20Sn binary eutectic. The microstructures of the Au20Sn solder on the Cu and Ni substrates could be controlled by using different bonding conditions. When the bonding condition was 290°C for 2 min, the microstructure of Au20Sn/Cu and Au20Sn/Ni was a two-phase (Au₅Sn and AuSn) eutectic microstructure. When the bonding condition was 240°C for 2 min, the AuSn/Au₅Sn/Cu and AuSn/Au₅Sn/Ni diffusion couples were subjected to aging at 240°C. The thermal stability of Au20Sn/Ni was better than that of Au20Sn/Cu. Moreover, less Ni was consumed compared to that of Cu. This indicates that Ni is a more effective diffusion barrier material for the Au20Sn solder.     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Influence of Bonding Temperature and Applied Load on the Bonding Integrity and Optical Performance of Face-Down Bonded Ridge-Waveguide Lasers

The effects of bonding temperature and applied load on the mechanical integrity of 80Au-20Sn solder joints and the optical performance of laser diodes (LDs) are presented. Insufficient solder wetting at 280°C and poor joint integrity at an applied load below 0.196 MPa resulted in solder failure during die shear test. As the bonding temperature and applied load increased, the joint integrity and the optical performance improved. Shear testing further showed fracture in the LD due to the high mechanical strength of 80Au-20Sn solder and good adhesion properties of the solder joint. Microstructure studies showed good metallurgical stability with little interfacial intermetallic compound (IMC) formed. However, beyond an applied load of 0.523 MPa, the LD performances degraded due to modification of the bandgap energy in the active region. From our experimentation, a bonding window with good bonding integrity and high optical performance was, nevertheless, achieved.     

Flip-Chip Bonding of MEMS Scanner for Laser Display Using Electroplated AuSn Solder Bump

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.     

采用金锡合金的气密性封装工艺研究

根据功率器件的气密性封装要求,设计了完整的金锡封焊工艺方法和流程,研究了工艺中的技术难点,提出了确保封装工艺稳定性和可靠性的技术要点.实验选甩Au80Sn20预成型焊环作为封接材料对器件进行气密性封装.通过大量试验得出了最佳工艺曲线(包括温度、时间、气氛和压力等).密封后的产品在经受各项环境试验和机械试验后,其结构完整性、电学特性、机械牢固性和封装气密性均能很好地满足要求,证明了采用倒置型装配的金锡封焊工艺的可行性及优越性.     

The influence of thermal aging on joint strength and fracture surface of Pb/Sn and Au/Sn solders in laser diode packages

The joint strength and fracture surface of Pb/Sn and Au/Sn solders in laserdiode packages after thermal-aging testing were studied experimentally. Specimens were aged at 150°C for up to 49 days. The joint strength decreased as aging time increased. The microstructure and fracture surface of the Pb/Sn and Au/Sn solder joints showed that the joint strength decrease was caused by both the enlargement of the initial voids and an increase in the number of voids as aging time increased. The formation of Kirkendall voids with intermetallic-compound (IMC) growth of the Pn/Sn solder as aging time increased was also a possible mechanism for the joint-strength reduction. Finite-element method (FEM) simulations were performed on the joint-strength estimation of Pb/Sn and Au/Sn solders in thermal-aging tests. The coupled thermal-elasticity-plasticity model was used to simulate distributions of the thermal and residual stresses, creep deformation, and joint-strength variations in the solder joints under various thermal-aging tests. Simulation results were in good agreement with the experimental measurements that the solder-joint strength decreased as aging time increased. The result suggests that the FEM is an effective method for analyzing and predicting the solder-joint strength in laserdiode packages.     

Characterization of 63Sn37Pb and 80Au2OSn solder sealed opticalfiber feedthroughs subjected to repetitive thermal cycling

A highly accurate prediction of hermeticity lifetime is made for eutectic 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber-Kovar ^TM nosetube feedthroughs subjected to repetitive thermal cycling. Thermal fatigue fracture of the Sn-Pb solder/Kovar^TM interface develops when cracks, initially generated from creep deformation of the solder, propagate gradually through the junction in the axial direction. A nonlinear axisymmetric finite element analysis of the 63Sn37Pb fiber feedthrough seal is performed using a thermo-elastic creep constitutive equation, and solder joint fatigue based on accumulated strain energy associated with solder creep imposed by temperature cycling is analyzed. Additionally, thermal effective stress and plastic strain is studied for alternative 80Au20Sn solder by the finite element method with results indicating significant increase in useful life as compared to 63Sn37Pb. SEM/EDX metallurgical analysis of the solder/Ni-Au plated Kovar^TM nosetube interface indicates that AuSn₄ intermetallic formed during soldering with 63Sn37Pb also contributes to joint weakening, whereas no brittle intermetallic is observed for 80Au20Sn. Hermetic carbon coated optical fibers metallized with Ni,P-Ni underplate and electrolytic Au overplating exhibit correspondingly similar metallurgy at the solder/fiber interface. Combined hermeticity testing and metallurgical analysis carried out on 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber feedthroughs after repetitive temperature cycling between -65 and +150°C, and -40 and +125°C validated the analytical approach     

Ag–Copper Structure for Bonding Large Semiconductor Chips

Ag–copper dual-layer substrate design is presented. The Ag cladding on the copper substrate is a buffer to deal with the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ppm/$^{circ}$C) and Cu (17 ppm/$^{circ}$ C). Ag is chosen because of its low yield strength, only one-tenth of that of Cu and one-third of the popular Sn3.5Ag solder. Other advantages are high electrical conductivity and high thermal conductivity. To bond Si chips to the Ag layer on copper substrates, Sn-rich solder is used. A fluxless bonding process is designed and developed. The bonding media are Ni/Sn/Au multilayer solder structure plated over Ag. In this design, Ni is a diffusion barrier between Sn and Ag. The thin (100 nm) outer Au layer prevents inner Sn from oxidation. The Si chip is deposited with Cr/Au under bump metallurgy (UBM). The bonding process is performed in 50-mtorr vacuum atmosphere without any flux. Comparing to bonding in air, the oxygen content is reduced by a factor of 15 200. The resulting joints consist of three distinct layers, i.e., Sn-rich layer, Ni$_{3}$ Sn$_{4}$ intermetallic compound, and Ni. Scanning acoustic microscopy (SAM) is used to verify the quality of the joint. Microstructure and composition of the joints are studied using scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX). This technique presents an initial success in overcoming the very large mismatch in thermal expansion between silicon and copper. It can be applied to mounting numerous high-power silicon devices to Cu substrate for various applications such as hybrid automotive and high-voltage power networks.      

Reliability study of new SnZnAl lead-free solders used in CSP packages

We have implemented a company-wide effort to progressively reduce the use of Pb(lead) and eventually eliminate this environmental pollutant from its products. As part of this effort, it has developed a new lead-free solder that consisting of Sn(tin), Zn(zinc), and Al(aluminum) and yet offers superior productivity and joint reliability. The new lead-free solder has a melting point equivalent to that of a SnPb eutectic solder, and enables devices to be packaged at a lower temperature than with the increasingly popular Sn(tin), Ag(silver), Cu(copper) solder. Thus, the new lead-free solder accelerates the elimination of Pb from products. we have already used printed circuit boards containing the new lead-free solder in some products, and plans to extend its use to other products.We further mounted SnZnAl solder balls onto Cu/Ni(nickel)/Au(gold) plated polyimide substrate at a joining temperature of 215 °C for CSP applications. It was confirmed that the joint interface between soldered ball and substrate at the initial stage was made of 2-layered compounds, i.e., AuZnSn on soldered side and ZnSnNi on substrate side. After 1000 h aging at 150 °C, the two layers compounds become one layer of ZnSnNiAu compound. No strength deterioration of Cu/Ni/Au/SnZnAl after the 1300 h shelf test was detected in the ball shear strength compared with the initial value. This paper describes the characteristics of the new lead-free solder and the results of a study on its solder ball CSP package.     

Thermal transient characteristics of die attach in high power LED PKG

The reliability of packaged electronics strongly depends on the die attach quality because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED PKG have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated for characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED PKG. From the differential structure function of the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding with the thermal resistance of about 3.5 K/W was much better than this of Ag paste and solder paste with the thermal resistance of about 11.5–14.2 K/W and 4.4–4.6 K/W, respectively. From this results, it is possible to fabricate high power LED with a small thermal resistance and a good die attach quality by applying Au/Sn eutectic bonding die attach with a high reliability and a good repeatability.     

Mechanical reliability of Sn-rich Au–Sn/Ni flip chip solder joints fabricated by sequential electroplating method

In this study, we evaluated the mechanical reliability of Sn-rich, Au–Sn/Ni flip chip solder bumps by using a sequential electroplating method with Sn and Au. After reflowing, the average diameter of the solder bump was approximately 80 μm and only a (Ni,Au)₃Sn₄ intermetallic compound (IMC) layer was formed at the interface. Due to the preferential consumption of Sn atoms within the solder matrix during aging, the solder matrix was transformed sequentially in the following order: β-Sn and η-phase, η-phase, and η-phase and ε-phase. In the bump shear test, the shear force was not significantly changed despite aging at 150 °C for 1000 h and most of the fractures occurred at the interfaces. The interfacial fracture was significantly related to the formation of brittle IMCs at the interface. The Sn-rich, Au–Sn/Ni flip chip joint was mechanically much weaker than the Au-rich, Au–Sn/Ni flip chip joint. The study results demonstrated that the combination of Sn-rich, Au–Sn solder and Ni under bump metallization (UBM) is not a viable option for the replacement of the conventional, Au-rich, Au–20Sn solder.     

Au20Sn箔材焊料及其应用

使用单辊法制备Au20Sn箔材,通过XRD衍射仪测试其晶态结构和相组成;采用差热分析法(DTA)测试其熔化温度;应用环境扫描显微镜(ESEM)观察其常温下微观组织。对比了单辊法制备的金锡焊料和叠层法制备的金锡焊料焊接光纤接头和大功率LED固晶接头的显微结构。结果表明:单辊法工艺可以制备Au20Sn箔材,其物理性能和显微组织都与理论的Au20Sn焊料一致;单辊法制备的金锡焊料的焊接性能比叠层法制备的焊料好。     

Fluxless Flip-Chip Solder Joint Fabrication Using Electroplated Sn-Rich Sn–Au Structures

A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn–Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn–Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn–Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au$_5$Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217$^circ$C–222$^circ$C. The plated Sn–Au solder bumps on silicon with 50$mu$m in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited.     

RF device package method using Au to Au direct bonding technology

This paper presents design, fabrication and evaluation of a wafer level MEMS (Micro Electro Mechanical System) encapsulation using an Au to Au direct bonding with wrinkle patterned layer. For the effective encapsulation, the optimal bonding condition, the bonding temperature 350 °C, the bonding pressure 58 MPa and the duration time 30 min, was developed and used in this paper. We briefly evaluated the bonding strength of test wafers after the bonding test. For RF (Radio Frequency) device packaging, we effectively interconnected Au CPW (Coplanar Waveguide) lines to feedthroughs and measured the RF characteristics. Measured insertion loss of the packaged CPW line was −0.11 dB at 2 GHz. The glass wafer having patterned Au sealing lines was also bonded and has been dipped in the acetone solution for 24 h to examine the leakage of bonding wafer. After 24 h dipping, any leakage point has not been observed at the sealing line and inside the cavity. These results showed that our Au to Au direct bonding method is very reliable and suitable for RF device packaging.