Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates

Strained-Si pMOSFETs on very thin relaxed virtual SiGe substrates are presented.The 240nm relaxed virtual Si0.8Ge0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 1e7cm－2.At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/（V·s）.Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET''''s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

采用薄SiGe虚拟衬底制备应变Ge材料

This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.     

Resonant cavity enhanced photoluminescence of tensile strained Ge/SiGe quantum wells on silicon-on-insulator substrate

The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.     

利用物理气相淀积工艺制备的HfTaON薄膜热力学稳定性研究

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope （HRTEM） and X-ray photoelectron spectroscopy （XPS）. The results indicate that the magnetron-sputtered HfTaON films on Si substrate are not stable during the post-deposition annealing （PDA）. HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfraON and Si substrate may effectively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric＇s equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric＇s equivalent oxide thickness.     

A VHF PECVD Micro-Crystalline Silicon Bottom Gate TFT with a Thin Incubation Layer

The incubation layer with amorphous structure between the substrate and crystalline layer may obviously affect the performance for a microcrystalline Si thin film transistor (μc-Si TFT),especially for the bottom gate TFT(BGTFT).It is found that decreasing the ratio of SiH4/（H2+SiH4） is an effective way to decrease the incubation layer thickness of μc-Si directly deposited by VHF PECVD without any further thermal or laser treatment.Based on the μc-Si with a thin incubation layer,the BG-TFT with Al/SiNx/μc-Si/n+μc-Si/Al structure is fabricated.The ratio of on-state current to off-state current is up to 10.6,the mobility is around 0.7cm2/（V·s）,and the threshold voltage is about 5V.     

Temperature dependent IDS-VGS characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si（llO） substrate

We fabricated n-type Si-based TFETs with a Ge source on Si（110） substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si（110） are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall （SRH） generation-recombination current of the n＋ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling （TAT） current and band-to- band tunneling （BTBT） current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.     

离子注入硅退火过程中平面形核和结晶问题研究

According to the thermodynamic and kinectic theory, considering variation of bulk free energy and superficial energy after nucleation as well as migration of atom, we study deeply planar nucleation and crystallization that relate to two possible transition mechanism in the process of annealing of ion implanted Si. 1） Liquid/Solid transition: critical nucleation work is a half of increased superficial energy and inversely proportional to the supercooling . Compared with bulk nucleation, the radius of critical nucleus decrease by a half, nucleation rate attain its maximum at T=1/2Tm; 2） Amorphous/Crystal transition: atoms containing in critical nucleus and on its surface, as well as critical nucleation work are all directly proportional to the height of nucleus, nucleation barrier is a half of superficial energy too. Taking SiGe semiconductor as an example, we calculate that the value of its elastic strain energy is 0.03eV/atom, and get more reasonable result after taking its effect to transition into account. In one word, we reach such a conclusion through calculation: for annealing of ion implanted Si, no matter what transition way—liquid or solid, the planar nucleation and recrystallization process is actually carried out layer by layer on crystal substrate, probability forming “rod-like”nucleus is much larger than probability of “plate-like”nucleus.     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

采用低温Si技术的Si/SiGe异质结P-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

Low-temperature relaxation of elastic stresses in SiGe/Si heterostructures irradiated with Ge<Superscript>+</Superscript> ions

Pseudomorphic Si_0.76Ge_0.24/Si heterostructures grown by molecular-beam epitaxy were irradiated with 350-keV Ge⁺ ions at a temperature of 400°C so that the peak of the ions’ energy losses was located within the silicon substrate (deeper than the SiGe-Si interface). The effect of ion implantation on the relaxation of elastic stresses and the defect structure formed as a result of postimplantation annealing is studied. It is found that annealing at a temperature even as low as 600°C makes it possible to ensure a very high degree of relaxation of elastic stresses in the heterostructure and a comparatively low density of threading dislocations in the SiGe layer (<10⁵ cm^?2). The results obtained make it possible to suggest a method for the formation of thin SiGe/Si layers that feature a high degree of relaxation, low density of threading dislocations, and a good surface morphology.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

The influence of carbon on the properties of Si/SiGe heterostructures

Si/SiGe/SiGe:C/SiGe/Si heterostructures are investigated by Raman spectroscopy, electroreflectance method, and secondary-neutral mass spectrometry. It is shown that doping of a SiGe layer lying between undoped SiGe layers with C (1.5%) leads to almost complete stress relaxation in the doped layer. It is found that high-temperature photon annealing is responsible for a partial stress relaxation in the lower SiGe buffer layer. However, such annealing increases the Si content in this layer. Low-temperature treatment in the radio-frequency (RF) hydrogen plasma leads to considerable stress relaxation in the lower buffer layer without varying its composition. The results obtained from the electroreflectance and secondary-neutral-mall spectra correlate with the Raman spectroscopy data.