Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.     

Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

A study on channel design for 0.1 μm buried p-channel MOSFETs

This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 μm via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed the substrate with a doping concentration of 1e17/cm³. By optimizing the doping structure, an attempt is made to investigate fundamental limits of the buried channel design. In concurrence with published results, it is shown that there is a maximum allowable thickness for the first layer, while the thickness of the anti-punchthrough layer has a minimum value in order to effectively suppress punchthrough. The above constraints enable devices with good subthreshold characteristics (subthreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation results show that it is possible to fabricate buried p-channel MOSFETs with n-type polysilicon gate electrodes in the 0.1 μm regime, it is also evident that advanced doping and low temperature fabrication technologies are needed that provide control over doped layers of ultra-thin dimensions     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

Fabrication and characterization of bipolar transistors within-situ doped low-temperature (800°C) epitaxial silicon

The authors report the fabrication of bipolar transistors at a maximum process temperature of 800°C, utilizing in situ doped low-temperature epitaxial silicon deposited by ultralow-pressure chemical vapor deposition (U-LPCVD), and their subsequent characterization. The epitaxial silicon layers form the collector, base, and emitter layers. To attain a high donor concentration in the epitaxial emitter layer, the U-LPCVD process is plasma enhanced. Transistors having excellent DC characteristics down to collector currents of ~10 pA/μm² are obtained, which indicates that the bulk quality of the epitaxial films is good enough for device fabrication     

0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

0.15-μm buried-channel p-MOSFETs with ultrathin boron-dopedepitaxial Si layer

We demonstrated silicon MOSFETs with a counter-doped ultrathin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with boron with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, and so it is easy to adjust the threshold voltage of the buried-channel p-MOSFETs with n-type polysilicon gates. It was confirmed that choosing an ultrathin epitaxial layer at 10 nm leads to suppression of the short-channel effects in buried-channel p-MOSFETs with gate length down to 0.15 μm, while maintaining an appropriate value of threshold voltage     

一种单层多晶硅BiCMOS工艺研究

介绍了一种单层多晶硅ＣＭＯＳ工艺。该工艺采用Ｐ型衬底,Ｎ型Ｐ型双埋层,Ｎ型薄外延结构,掺杂多晶硅作为ＣＭＯＳ晶体管栅极和双极ＮＰＮ晶体管的发射极。ＣＭＯＳ晶体管采用源漏自对准结构,钛和铝双层金属作为元件互连线,ＰＥＣＶＤＳｉＮｘ介质作为钝化薄膜。     

In-situ epitaxial silicon—oxide-doped polysilicon structures for MOS field-effect transistors

Limited reaction processing (LRP) has been used to achieve the in-situ growth of epitaxial silicon-oxide-doped polysilicon layers. The in-situ growth of these multiple layers was combined with the selective epitaxial growth technique to create structures for MOSFET fabrication. The results of n- and p-channel transistor fabrication utilizing these structures are presented.     

Novel in-situ doped polysilicon emitter process with burieddiffusion source (BDS)

An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 μm×0.25 μm and with nearly ideal I -V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 μm×4.0 μm     

Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias $V_{rm bg}$, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). $V_{rm bg}$ only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 $hbox{V}/muhbox{m}$ of the conventional SOI to 457 $hbox{V}/muhbox{m}$ at $V_{rm bg} = hbox{0 V}$, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.      

Low-threshold continuous-wave surface emitting lasers with etchedvoid confinement

Data are presented demonstrating low threshold continuous wave operation of AlAs/GaAs/InGaAs vertical cavity surface emitting lasers. Continuous wave thresholds of 470 μA have been realized for device diameters of ~4 μm, and 1.1 mA for a device diameter of 10 μm. A two-step molecular beam epitaxial growth process is used which results in a buried etched void surrounding the active cavity of the laser     

A new concept of p-(n-)/p-(n ) thin-film epitaxial silicon wafers for MOS ULSI's that ensuresexcellent gate oxide integrity

A new concept of epitaxial silicon (Si) wafers (NC epi) in which p ^-(n^-) thin-film layers are grown on p^-(n^-) Czochralski (CZ)-Si substrates (substrate resistivity: approximately 10 Ω cm) is proposed for metal oxide semiconductor (MOS) ultra large-scale integrated circuits (ULSI's) as a starting material. A thickness of 0.3-1 μm for the epitaxial layer (p ^-/p^- structure) is shown to be sufficient for improving the gate oxide integrity for MOS-ULSI's. The epitaxial layer grown on Si substrate greatly reduces weak spots in the gate oxide layer by covering microdefects in the CZ-Si represented by the crystal originated particle (COP). The p^-/p^$thin-film epitaxial structure results in very controlled resistivity for the electrically active region in the device, which in turn results in a lower growth cost and higher feasibility for use in current ULSI's. The features of NC epi in combination with proximity gettering is presented. An application of NC epi in shallow-trench isolation processes is discussed, considering the retrograde-type well-tub. The amenability of epitaxial wafers to wafer enlargement (over 300 mm) is discussed to eliminate the bad effects of COP     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization     

Simox technology and its application to CMOS LSIS

SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.     

Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-/spl mu/m-deep with 2-/spl mu/m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 /spl Aring/ of thermal silicon-dioxide film and 2/spl mu/m of polysilicon film. The sheet resistances of N/sup +/ and P/sup +/ diffusion and N/sup +/ -doped polysilicon layers were reduced to 3 to 4 /spl Omega//spl square/ by using the self-aligned TiSi/sub 2/ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi/sub 2/ layer. The 0.5-/spl mu/m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi/sub 2/ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static /spl divide/ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.     

Improvement of RCA transistor using RTA annealing after theformation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 × 8 μm². The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

InGaAsP (λ=1.3 μm) strip buried heterostructure lasersgrown by MOCVD

The authors describe InGaAsP-InP index guides strip buried heterostructure lasers (SBH) operating at 1.3 μm with a 1.1-μm guiding layer grown by a two-step atmospheric pressure metalorganic chemical vapor deposition (MOCVD) growth procedure. These lasers are compared with buried heterostructure lasers having similar guiding layers under the active layer but terminated at the edge of the active layer. SBH lasers with 0.15-μm-thick active layer strips, 5-μm wide, and guide layers varying from 0 to 0.7 μm have threshold currents increasing from 34 to 59 mA, and nearly constant differential external quantum efficiencies of 0.2 mW/mA. The threshold current increases more rapidly with temperature with increasing guide layer thickness, with T₀ decreasing from 70°C for lasers without a guide layer to 54.3°C for lasers without a guide layer to 54.3°C for lasers with 0.7-μm-thick guide layers. Output powers of up to 30 mW/facet have been obtained from 254-μm-long lasers and were found to be insensitive to guide layer thickness