面向LTE-A终端软基带的矢量处理器设计

面向移动终端处理器的低功耗、低成本、高效率、灵活升级的需求,本文在对LTE-A基带算法并行性分析的基础上,提出了一种基于超长指令字（Very Long Instruction Word,VLIW）和单指令多数据（Single Instruction Multiple Data,SIMD）混合结构的矢量处理器作为终端软基带解决方案.该矢量处理器采用变长的VLIW指令字,共有7条矢量数据通路,每条通路可执行16个16bit的定点运算;采用分组的系数存储器提高灵活性,受限访问的寄存器组降低电路面积;同时设计了SHUF和ISHUF指令专门用于快速傅里叶变换（FFT）和雏特比（vIT-ERBI）译码算法的矢量化实现.最后本文实现和分析了FFT和VITERBI译码算法.     

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit

An embedded test stimulus decompressor is presented for the test patterns decompression, which can reduce the required channels and vector memory of automatic test equipment (ATE) for complex processor circuit. The proposed decompressor mainly consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly and efficiently. In order to reduce the number of test patterns and configurations, a test patterns compaction algorithm, using CI-Graph merging, is proposed. With the proposed periodically alterable MUX network and the patterns compaction algorithm, smaller test data volume and required external pins can be achieved as compared to previous techniques     

双处理机终端控制器的信道16微处理器

介绍了双处理机终端控制器（DPTC）的信道16微处理器的组成部分及工作原理。该微处理器简化了一般微处理器的功能,增加了通信电路所持有的信道计算和接口自动选择等功能。它的整个电路是动态的,面积和功耗均很小。用Cadence的Verilog-XL对其进行仿真,获得了预期的效果。     

SIMD图像处理机存储系统研究

为了获得尽可能高的并行计算单元的计算能力,对SIMD图像处理机的存储系统进行了深入研究.该存储系统根据图像处理应用的特点,使用基于编译获得的数据流存取全局信息进行数据流调度,有效地提高了数据存取的速度,满足了并行计算单元对数据存取速度的要求,为SIMD图像处理机系统性能的提高提供了支持.     

目标数据存储控制单元的ASIC化设计

文章在分析目标数据存储控制单元工作原理的基础上，提出了用ＦＰＧＡ芯片设计该单元的具体思路和方法，以及在设计中应考虑的问题，最后，给出了实验结果。     

基于ARM处理器的LED可变情报板嵌入式控制器

从智能交通系统(ITS)信息显示服务子系统的需求出发,通过分析LED可变情报板与一般LED室内、室外显示屏的区别,阐述了LED可变情报板的特点,提出了LED可变情报板控制器的功能要求,并利用ARM7TDMI-S系列的LPC2210-PACK微处理器设计了一款LED可变情报板嵌入式控制器。     

基于Nios处理器的FED控制系统设计

FED是新一代真空平板显示器件,具有色彩自然逼真、响应速度快、宽视角、低功耗、矩阵选址等突出优点,应用范围广泛。FED显示控制系统是整个驱动电路的核心,随着分辨率和规模化的提高,需要高速的帧存储器和高速的接口,加速系统的运行速度,减少传输时间。主要介绍了一种采用Nios软核作为中央处理器,进行主要的计算处理、控制各种信号的FED显示控制系统。同时使用FPGA作为协处理器,把一些运算中常用到的耗用大量CPU时钟的运算以Nios软核的形式嵌入到系统中,利用动态可重构的原理实现各个软核函数的分时复用,提高了整个FED控制系统的性能。     

A Universal Vector Controller for Four-Quadrant Three-Phase Power Converters

Power factor corrected (PFC) rectifiers, active power filters (APFs), static VAR compensators (STATCOM), and grid-connected inverters (GCI) are indispensable elements in distributed generation power systems. PFC rectifiers are essential for load side harmonic and reactive power correction, APFs can suppress the harmonics generated by nonlinear loads or sources, STATCOMs can control the power flow in the grid, while GCIs are the key elements bridging the renewable energy sources and the power grid. Previous theory and experiments have demonstrated that one-cycle control is capable of controlling all above mentioned three-phase converters, featuring excellent performance, simple circuitry, and low cost. This paper further unifies the control key equations for the previously mentioned converters, which results in a universal solution that realizes all these functions with a same controller. The concept has been verified by a 1-kVA prototype and supported by a series of experimental results     

基于Nios处理器的模糊控制器设计

采用具有并行和串行处理方式的Nios处理器来设计基于推理算法的模糊控制器.从模糊推理算法的特征出发,对算法中并行处理的部分定义了相关的自定义指令;按照整个算法流程的串行特性设计模糊子函数.充分利用了Nios处理器的两种处理方式,并将其有机结合,提高了糊控制器的实时性和灵活性.     

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

Fully Pipelined Soft Vector Processor as a CPU Accelerator

FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations. Compared with Central processing unit (CPU), Digital signal processor (DSP), Altera C2H tool and OpenCL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively.     

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.      

基于单片机沥青洒布量控制器的设计

随着高速公路和市政建设的发展,沥青洒布车也越来越普及,但沥青洒布车控制多数采用电气控制来实现,并且辅助于人工来完成铺洒沥青。该文根据沥青洒布车洒布量控制器的工艺要求,采用以单片机89s52为控制核心,输出以PWM驱动方式的沥青矢量泵控制量,采用多个8155扩展电路来实现,驱动48个沥青喷嘴的电磁阀,并利用8279键盘接口芯片来实现人机交互界面和显示运行状态下各种工作参数和变量。该控制器设计简单、操作方便,能够对沥青洒布量进行精确有效的自动控制,具有较高的性价比。     

一种可编程嵌入式异步SRAM存储控制器

介绍了一种可编程嵌入式异步SRAM存储控制器的设计与实现方法。从SRAM读写协议、总体设计、各子模块的设计、模拟验证、FPGA实现，及其在数字视频系统中的应用等各个角度，对SRAM控制器的设计方法作了较为全面的介绍。这种设计方法可广泛应用于ASIC芯片、SOC系统等需要嵌入存储控制器的场合。     

高速数字信号处理器扩展存储空间的设计方案

基于TI公司的高速数字信号处理器芯片．详细描述美国SST公司推出的28SF040闪存芯片的性能特点、引脚功能，同时给出用其扩展DSP芯片的程序存储器空间的硬件设计电路与软件编程方法。     

The Development of a Bubble Memory Controller for Low-Cost FiIe Use

The bubble memory has several features such as low-cost low-power consumption, small physical size, high reliability, and non-volatility, which make it suitable for low-cost microcomputer files. The microcomputer interface and bubble control logics are integrated into a single chip which we call the bubble memory controller (BMC), making it possible to install a complete 1 Mbit bubble memory system on a 15 cm X 18 cm board. This paper describes in detail the BMC development and considers important matters in the design of large-scale logic LSI's which are represented by the microprocessors.     

基于ARM处理器的TSC2046触摸屏控制器的应用

触摸屏技术经过十几年的发展已经成为一种方便、经济的人机界面输入手段。TSC2046是四线电阻式触摸屏控制器,其核心是一个具有采样和保持功能的12位逐次逼近式A/D转换器。以飞利浦公司的ARM芯片为基础,通过TSC2046触摸屏控制器和四线电阻式触摸屏构成硬件基础,在此基础上,开发了触摸屏面板控制程序。该触摸屏已应用于实际项目中,触摸效果良好。     

基于CN56xx网络处理器的网络控制器的研究

在网络处理器的平台上开发了用户管理控制系统,用于对用户上网内容和行为进行监控.网络处理器是可编程的高效网络数据处理芯片,网络控制器是用户管控系统中用于过滤数据的器件.通过实验,在硬件方面使用优化流水线这一高效的芯片处理数据的方法来提升数据处理效率,在软件方面通过使用不同的算法来优化性能,这些算法包括流过滤算法、潜在语义索引算法和IP碎片处理技术.实验结果表明,基于网络处理器的网络控制器在根据过滤和转发规则对数据过滤和转发时准确率高,速度快,非常好地达到了对用户上网内容和行为监控的效果.     

基于FPGA的SD卡控制器设计

以FPGA为平台,设计了采用SPI接口的SD卡控制器.整体设计用Verilog HDL硬件描述语言实现,同时采用数据缓存(First In First Out,FIFO)技术解决实际应用中的时序问题,最终实现了整体设计功能.本设计充分发挥了FPGA所具有的开发周期短、处理能力强等特点,已成功应用于音频芯片采集的数据存储...     

带闪存的嵌入式电机控制器ADMCF328

电机控制DSP芯片是以DSP为内核并辅以完备的电机控制外设来实现电机控制的专用DSP器件，它减少了系统中传感顺的数量，并能依据控制来产生PWM信号，因而适应于应用单处理器的多电机控制系统，文中介绍了一种廉价的电机控制专用DSP芯片ADMCF328的特性、基本结构、引脚功能以及具体应用。