Two-dimensional self-consistent simulation of a triangular p-channel SOI nano-flash memory device

This paper presents the simulation of an SOI nano-flash memory device. The device is composed of a triangular quantum wire channel p-MOSFET with a self-aligned nano-floating gate embedded in the gate oxide. The simulation is carried out by combining TSUPREM-4 and a two-dimensional (2-D) self-consistent solution of the Poisson and Schrodinger equations. The fabrication process as well as quantum physics are taken into account. Hole distribution in the inversion layer of the triangular channel section is calculated in terms of wave functions and energy subbands. The threshold voltage shift between the programming and erasing of the device is investigated. In this paper, we show that the channel shape plays a crucial role in the programming voltage and the threshold voltage shift. Based on the fact that the holes are confined mainly at the top of the triangular channel section, we explain why our triangular channel device can be operated at relatively low programming voltage despite of a thick gate oxide and tunnel oxide. The threshold voltage shift in the triangular channel device is compared with that in a rectangular channel device. The result shows that the triangular channel device exhibits the larger threshold voltage shift.     

Multi-bit organic ferroelectric memory

Storage of multiple bits per element is a promising alternative to miniaturization for increasing the information data density in memories. Here we introduce a multi-bit organic ferroelectric-based non-volatile memory with binary readout from a simple capacitor structure. The functioning of our multi-bit concept is quite generally applicable and depends on the following properties for the data storage medium: (a) The data storage medium effectively consists of microscopic switching elements (‘hysterons’). (b) The positive and negative coercive fields of each hysteron are equal in magnitude. (c) The distribution of hysteron coercive fields has substantial width. We show that the organic ferroelectric copolymer P(VDF-TrFE) meets these requirements. All basic properties of our device were measured and modeled in the framework of the dipole switching theory (DST). As a first example we show the possibility to independently program and subsequently read out the lower, middle and upper parts of the hysteron distribution function, yielding a 3-bit memory in a single capacitor structure. All measured devices show good state reproducibility, high endurance and potentially great scalability.     

Integration technology for ferroelectric memory devices

Ferroelectric devices have been developed for future memory devices due to their ideal memory properties such as non-volatility, fast access time, and low power consumption. Several integration issues for commercial ferroelectric devices have been overcome or are being resolved by novel process technology and design technology. The process technology is combined with ferroelectric material technology, electrode technology, etching technology, hydrogen barrier technology, barrier and plug technology, and backend technology. The advanced process technologies are enhanced by developing its own design technology. In recent few years, low density ferroelectric random access memory (FRAM) products start to gradually but progressively penetrate into memory and smart card market, and the ferroelectric devices are developed to 32 Mb FRAM with 0.25 μm design rule and triple metallization. In this paper, it is reviewed how to integrate the ferroelectric devices for producing commercial products.     

Modeling ferroelectric capacitors for memory applications

The ferroelectric capacitor model is the foundation for accurate simulation of ferroelectric hysteresis loops and minor loops, transitions between the loops under arbitrary voltage patterns, transient responses of ferroelectric capacitors to short voltage pulses with widths in the nano-second range, and temperature behaviors of ferroelectric capacitors. The simulation speed is the same as that for a typical nonlinear capacitor. To the circuit designers, a ferroelectric capacitor is represented as a two-port device like a capacitor. The parameters are extracted easily and reliably by curve fitting the measured hysteresis loops. The model is applicable to fast circuit simulations for large ferroelectric memory designs.     

Two-dimensional simulation of silicon avalanche cathodes

The characteristics of silicon avalanche cathode as a novel electron emitting device with ultra-shallow p-n junctions have been studied using the two-dimensional device simulator PISCES-IIB. The steady-state simulation indicates that the nonplanar surface topology resulting from fabrication process causes current crowding near the edge of the emitting area where the surface step exists. Current crowding degrades the emission uniformity and also reduces the emission current under increased reverse bias. The nonplanar surface structure also causes punchthrough in the epitaxial layer as the reverse bias on the cathode increases. As a result, the percentage of the cathode current contributing to emission decreases, reducing the emission efficiency consequently. The simulation shows that the portion of the cathode current that flows through the emitting area drops to as much as 30% at cathode bias higher than 12 V, compared to the same current just after breakdown. This also affects the rate of increase in the total emission current which is the product of the emission efficiency and the overall cathode current     

Two-dimensional avalanche simulation of collector-emitter breakdown

A two-dimensional (2-D) transient simulation approach with the avalanche effect included has been used to study breakdown phenomena in conventional vertical bipolar transistors of the n-p-n type. The simulated current responses to voltage ramps show the important difference in speed for the emitter-collector breakdown and collector-base breakdown. DC specified values may be too conservative     

A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor

The ferroelectric field effect has successfully been demonstrated on a bulk semiconductor (silicon) using a thin ferroelectric film of bismuth titanate (Bi4Ti3O12) deposited onto it by RF sputtering. A new memory device, the metal-ferroelectric-semiconductor transistor (MFST); has been fabricated. This device utilizes the remanent polarization of a ferroeletric thin film to control the surface conductivity of a bulk semiconductor substrate and perform a memory function. The capacitance-voltage characteristics of the metal-ferroelectric-semiconductor structure were employed to study the memory behavior. The details of the study together with a preliminary results on the MFST are presented.     

A quasi-matrix ferroelectric memory for future silicon storage

We proposed a new quasi-matrix ferroelectric memory for use in future silicon-storage media. The memory unit consists of multiple ferroelectric capacitors and one access transistor. Each capacitor stores 1 bit of data, and the access transistor is shared by several capacitors. Compared with conventional crosspoint matrix type FeRAMs, which cause a signal degradation by read/write disturbance, this memory limits the disturbing frequency to an acceptable level by accessing the memory unit as a whole. Crosstalk noise was also minimized by applying a unique access scheme. This memory has a scalability by adopting built-in sense circuits, and enables an extremely high packing density with three-dimensional multistacking structures of memory cells.     

Operation of single transistor type ferroelectric random access memory

Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the 1T type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.     

Two-dimensional simulation for resonant tunneling transistor

A new two-dimensional device simulation for the resonant tunneling transistor is presented. In the simulation, the one-dimensional Schrodinger equation is solved for the intrinsic area of the transistor and the conventional two-dimensional drift-diffusion equations are solved for the extrinsic part. Both equations are coupled with the carrier generation-recombination term in the drift-diffusion equations. In addition, the Poisson equation is also solved self-consistently with them to take the charge distribution effect into account. The two-dimensional simulator has been successfully applied to the analysis of a resonant tunneling transistor and it was found that the current-voltage characteristics sensitively depend on the base resistance. This means that a two-dimensional treatment of the voltage drop in the base region is essential for an accurate simulation     

A ferroelectric associative memory technology employing heterogate FGMOS structure

A ferroelectric associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the ferroelectric memory cell to associative processing circuits, a heterogate floating-gate MOS structure has been developed. As a result, nondestructive reading of analog data written in the ferroelectric film has been made possible, allowing a wide voltage range of input signals to associative processing circuits. The concept has been experimentally verified using fabricated test devices and circuits.     

Why is nonvolatile ferroelectric memory field-effect transistorstill elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed     

Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

Device modeling of ferroelectric memory field-effect transistor (FeMFET)

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.     

Monte Carlo simulation of substrate enhanced electron injection in split-gate memory cells

In this paper, we use fullband Monte Carlo simulations and gate current measurements to investigate charge injection in split-gate memory cells under negative substrate bias. It is shown that, in the source-side-injection (SSI) regime, the enhancement of the programming efficiency due to the substrate bias is low, unless very low drain and floating-gate biases are considered. In particular, the enhancement of the efficiency is largely reduced if the drain current is kept constant when comparing different substrate biases. Furthermore, it is observed that the carrier injection profile under negative substrate bias is broader than in the SSI regime, and a substantial amount of charge is injected in the spacer region.     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

Two-dimensional simulation of constricted-mesa InGaAsP/InPburied-heterostructure lasers

A fully two-dimensional self-consistent numerical model of the steady-state behavior of 1.3 μm constricted-mesa InGaAsP/InP buried-heterostructure lasers is presented. Devices operating at this wavelength are very temperature sensitive and therefore the model for the first time includes coupled solutions to the thermal as well as the electrical and optical equation sets. The temperature dependence is included in the Fermi-Dirac statistics, bandgaps, mobilities, densities of states, Auger recombination coefficients, intervalence band absorption, optical gain, and thermal conductivities. The lasing mode profiles, carrier distributions, threshold currents, and temperature characteristics are analyzed and good agreement is found with experimental results, including the temperature dependence of the threshold current and the prediction of a break-point temperature. The optimum design parameters are investigated for reduced threshold currents, and the effect of optical loss in the blocking regions on lateral-mode control is analyzed     

Two-dimensional simulation of orientation effects in self-alignedGaAs MESFETs

The stress-induced orientation effects in self-aligned GaAs MESFETs were studied using a two-dimensional analysis. Devices oriented along different crystal directions, with different gate lengths, and under different stress conditions were studied. It was found that the piezoelectric effect caused by the surface stress plays a very important role in the device characteristics of short-channel self-aligned MESFETs. Structure parameters such as lateral spreading of N⁺ ions and p-type impurity concentration in the substrate were found to have great influence on the short-channel effect as well as the orientation effect. The short-channel effects can be suppressed and the device performance improved if the devices are oriented in the right direction and the structure of the devices and the thickness of the surface dielectric layer are properly chosen     

Two-dimensional simulation of conducted currents characteristics inelectrical discharges

In this paper, a simple general electrical discharges circuit model for electrical discharge current waveform simulation in overvoltaged air gaps is presented. A macroscopic circuital method of simulation utilizing the standard SPICE network simulator, based on a two-dimensional (2-D) nonlinear impedances network has been proposed. The structure of the simulation framework is designed to take into account the electrode geometries in a straightforward way. A study of conducted current waveform for different electrode geometries has been done. Experimental data have been used to validate the simulation results     

Two-dimensional simulation of thermal runaway in a nonplanarGTO-thyristor

The problem of electrothermal stability due to different cooling conditions has been investigated by computing the thermal transients in a nonplanar GTO-thyristor. In the first simulation, a steady state occurs with a heat sink removing all the dissipated power. In the second simulation severe thermal runaway is induced due to bad cooling conditions, allowing the analysis of destructive electrothermal interaction. The simulations are based on an advanced model for self-heating effects in silicon devices derived from first principles of irreversible thermodynamics. Self-consistently incorporating a phenomenological model of band gap narrowing in order to take account of heavy doping effects. The system of governing equations is valid in both the steady state and the transient regimes. Four characteristic effects contributing to the heat generation can be identified: Joule heating, recombination heating, Thomson heating, and carrier source heating. Thermal runaway is significantly accelerated in the simulations based on the thermodynamic model of thermoelectric transport compared to a conventional heuristic theory of thermoelectricity. The importance of the entropy balance equation is emphasized in order to derive the mathematical form of the heat flux and the current relations for electrons and holes. Limitations of underlying assumptions are discussed. It is shown that the heat generation implies the Thomson relations