Modified feedback ECL gate for Gb/s applications

This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference voltage and finds application in digital optical links in which data is typically transmitted single ended. The gate is compared with FECL and ECL gates, and its application to realize logic functions is discussed. A 6-Gb/s series gated decision circuit and a 2-Gbaud/s four-channel optical receiver array employing modified FECL gates are also described     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50-Ω/5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1-μm gate-length (F_τ=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations     

Design considerations for very-high-speed Si-bipolar IC's operatingup to 50 Gb/s

In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links     

All-Optical Binary Pattern Recognition at 42 Gb/s

In this paper, a programmable binary pattern recognition system that also indicates the temporal position of the matched target sequence is described. The system employs all-optical logic gates, and the number of gates required by the system is independent of the length of the target bit sequence. Experimental results with 42.6 Gb/s input data and target patterns up to 256 bits in length are presented.      

12Gb/s 0.25μm CMOS低功耗1:4分接器

实现了一种能运用于光传输系统SONET OC-192的低功耗单级分接器,其工作速率高达12Gb/s.该电路采用了特征栅长为0.25μm的TSMC混和信号CMOS工艺.所有的电路都采用了源极耦合逻辑,在抑制共模噪声的同时达到尽可能高的工作速率.该分接器具有利用四分之一速率的正交时钟来实现单级分接的特征,减少了分接器器件,降低了功耗.通过在晶圆测试,该芯片在输入12Gb/s长度为231-1伪随机码流时,分接功能正确.芯片面积为0.9mm×0.9mm,在2.5V单电源供电的情况下的典型功耗是210mW.     

Over 10 Gb/s regenerators using monolithic ICs for lightwavecommunication systems

The design and performance of repeater circuits based on Si and GaAs MESFET process technologies are described. Repeater circuits were designed and fabricated for around 10 Gb/s repeater systems using Si and GaAs IC processes. The Si ICs operated up to 9 Gb/s, and the GaAs ICs exceeded 10 Gb/s. It was verified that regenerative repeater systems using these ICs and optical amplifiers exhibit a stable operation at 10 Gb/s. The performance of the 10 Gb/s repeater using these monolithic ICs and photonic circuits is discussed     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optictransmission

We report a new integrated circuit for multiplexing and demultiplexing at rates of 100 Gb/s. In transistor multiplexer/demultiplexer circuits, the operating data rate is limited by transistor bandwidth. The demonstrated circuit, which uses terahertz Schottky diodes, readily attains the necessary bandwidths. The IC, based in the diode nonlinear-transmission line (NLTL) technology, consists of an array of four sample-hold gates driven by NLTL strobe generators. To permit use in multiplexing, the sample-hold gates use a six-diode configuration with 150 GHz output bandwidth. Initial measurements with simple data patterns at 104 Gb/s are demonstrated     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.      

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.     

Modeling and evaluation of positive-feedback source-coupled logic

Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-/spl mu/m CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation.