一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真. 该电路采用了0.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真.该电路采用了O.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

离子注入对插入损耗和隔离度影响的研究

基于一个典型的013 μm绝缘体上硅,射频开关电路工艺流程,分析了离子掺杂工艺流程对射频开关导通电阻Ron和关断电容Coff的影响。通过N型MOS管的浅掺杂注入后热退火温度和N型MOS管浅掺杂能量的分批实验,证实了退火温度可影响射频开关的导通电阻和关断电容。进一步实验结果显示,浅掺杂注入的砷（As）和磷（P）注入的剂量是主导因素,各自对导通电阻和关断电容值的影响均为线性且趋势相反,为基于013 μm SOI的射频开关性能的优化提供了依据。     

采用负反馈结构设计的高性能MOS开关

采样保持电路是高速高精度模/数转换器的重要组成部分。采样保持电路中的MOS开关的性能会影响到整个系统的信噪比(SNR)和信号噪声及失真比(SNDR)等各项指标。本文设计的负反馈结构,实现了MOS开关的导通电阻和输入信号无关,同时还采用了电容充放电技术,极大程度上减小了开关在采样过程中对信号的影响。     

平衡半桥D类放大器

一．D类放大器失效的主要原因 目前,实用的D类放大器,无论是集成电路还是分立元件,开关输出级全部采用了半桥或全桥结构。这种桥式电流开关是两个MOS管串联后直接跨接在正负电源两端,或电源两端与参考地之间。正常情况下,两个MOS管是轮流导通的,关闭的MOS管起限流和防止电源短路的保护作用,这是理想的状态。实际上由于开关管的延迟效应、储存效应等参数的差异,以及死区时间设计过小等因素,都会引起两个MOS管同时导通,这时灾难就发生了。MOS管的导通电阻很小,只有几十到几百111Q,这么小的电阻跨接在电源两端上,一个很大的电流将引起电源短路,这种现象叫通溃（ShootThrough）。     

一种基于电荷泵改进型CMOS模拟开关电路

提出了一种基于电荷泵的模拟开关结构.该结构使用电荷泵抬升MOS管的栅电压,从而大大改善开关的导通能力、线性度和动态传输范围.通过仿真验证了开关电路性能,结果表明设计的开关电路在电压0-5V范围内,导通电阻很小且信号损耗很小无失真.因而特别适用于低压系统.     

适于低电源电压应用的新型MOS自举采样开关

提出了一种适合低电源电压应用的新型MOS自举采样开关电路.通过“复制”自举电容和采样开关作为电荷损耗检测电路,并将检测出的电压降低值重新加到自举电容上,解决了传统MOS自举采样开关在低电源电压下工作时的电荷分享问题.基于0.18μm标准CMOS工艺,对电路进行了仿真.结果显示,在输入频率为60 MHz、峰-峰值为1V、采样频率为125 MHz时,与传统自举采样电路相比,新型自举采样电路采样开关管具有更低的导通电阻,无杂散动态范围( SFDR)提高了8dB,特别适合在低压高速A/D转换器中使用.     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.     

A Novel Clock Feedthrough Frequency Compensation forFast-Settling of Folded-Cascode OTA

基于有源开关电容网络二阶系统最小建立时间（MST）理论和阶跃响应分析，提出了一种用于Folded-Cascode放大器的频率补偿新方法，即通过MOS电容引入时钟馈通以调整电路阻尼因子η, 使其达到MST状态，从而实现快速建立. 研究结果表明，补偿后放大器的建立时间缩短了22.7%；当负载电容从0.5变化至2.5pF，其建立时间从3.62ns近似线性地增长到4.46ns；将采用该补偿方法的放大器应用于可变增益 (VGA)系统，当闭环增益变化时，仅需调整MOS电容值仍可实现对应状态下的快速建立.     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.     

10bit 20MS/s流水线模数转换器设计

设计了一个20MHz采样率,10bit精度流水线模数转换器。采用新颖的栅压自举开关,使电路在输入信号频率很高时仍具有良好的动态性能;用MATLAB仿真增益增强型运算放大器在不同反馈因子下闭环零、极点特性,提出了使大信号建立时间最短的主运放、辅助运放单位增益带宽和相位裕度范围。采用SMIC0.35μm2P4M工艺流片验证,20MHz采样率,2.1MHz输入信号下,SFDR=73dBc,ENOB=9.18bit。     

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).     

MOS IC crosspoint switch for space division digital switching networks

An MOS IC crosspoint switch for space division digital switching network is described. A sense amplifier for compensation of signal attenuation through the MOS IC switch is also considered. Transmission of a 50-100 Mbit/s bit rate digital signal seems a reasonable design objective on the basis of analysis of a preliminarily fabricated MOS IC switch and the design characteristics of a bipolar IC sense amplifier. The MOS switch and the SA are monolithic integrated. Dynamic test of the subsystem, in which MOS IC switches and bipolar IC SA's are connected in cascaded stages, has indicated that they are capable of 100 Mbit/s return to zero digital signal transmission and 46-dB signal-to-noise ratio.     

5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-/spl mu/m CMOS process

Two single-pole, double-throw transmit/receive switches were designed and fabricated with different substrate resistances using a 0.18-/spl mu/m p/sup $/substrate CMOS process. The switch with low substrate resistances exhibits 0.8-dB insertion loss and 17-dBm P/sub 1dB/ at 5.825 GHz, whereas the switch with high substrate resistances has 1-dB insertion loss and 18-dBm P/sub 1dB/. These results suggest that the optimal insertion loss can be achieved with low substrate resistances and 5.8-GHz T/R switches with excellent insertion loss and reasonable power handling capability can be implemented in a 0.18-/spl mu/m CMOS process.     

Design of Track/Hold （T/H） Circuit of Broad Bandwidth and High Speed Pipeline Structure ADC Based on the Super Frequency Application

A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture uncertainty, switch capacitor, and MOS switch, are analyzed. In the circuit, the full-differential structure and the bottom plate sampling technique are adopted to optimize the switch capacitors and MOS switches. The result based on the Spectre simulation on 0.35pm Bi- CMOS technology indicate that the aperture uncertainty, charge-injection, and non-linearity of clock feed-through are considerably restrained and the performance of T/H circuit is enhanced     

RFI-induced distortion in switched-capacitor circuits

The errors which are induced by radio-frequency interference (RFI) in switched-capacitor (SC) circuits are discussed and the main role played by the distortion of MOS switches in the on-state is highlighted. Furthermore, a new simple analytical model, which enables one to predict RFI-induced errors in SC circuits is proposed and it is validated by the comparison of its predictions with time-domain computer simulation results.     

A digital readout technique for capacitive sensor applications

The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3-μm CMOS technology. Detection of percent differences of <0.5% on 20-100-fF capacitors has been successfully demonstrated     

Small-signal optimization approach to design of microwave signal switch ICs on MOS transistors

This paper presents a technique for optimizing small-signal parameters of monolithic microwave signal switches on MOS transistors. The technique is based on analytical expressions and visual plots that allow us to determine the topological sizes of transistors providing the optimal values of insertion losses and isolation (decoupling). The effect of the parasitic inductance of connecting bondwires on the characteristics of signal switches is investigated; it is shown that parasitic inductance has a minor effect on insertion losses and reflection losses, but causes severe degradation of isolation. Based on the proposed technique, an IP block for a monolithic microwave switch, which can be used as an antenna switch or a composite functional block in multibit step phase shifters and S- or C-band attenuators, is designed. The comparative results of the numerical simulation and experimental investigation of the 0.25 µm CMOS IP block are presented; at the frequency of 1 GHz, the block has an upper linearity bound of at least +17 dBm, insertion losses of not more than 0.6 dB, and isolation not worse than -37 dB.     

A coplanar CMOS power switch

A 300 V power switch in a high-voltage CMOS technology compatible with a low-voltage MOS/bipolar technology is presented. This circuit can switch positive and negative 150 V pulses with rise and fall times of 100 ns for a 200 pF capacitive load. The switch has a low-voltage input control (/spl plusmn/15 V). Using earth-symmetrical non-overlapping high-voltage pulses as dynamic supply voltages, it is possible to reduce the power dissipation during the switching time considerably in comparison with the power dissipation of power switches, which use static (i.e., constant) supply voltages under the same conditions.