High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

Low-cost, high-efficiency, and high-speed SiGe phototransistors in commercial BiCMOS

We present a new approach to obtain low-cost and high-performance SiGe phototransistors in a commercial BiCMOS process. Photoresponsivity of 2.7 A/W was obtained for 850-nm detection due to the transistor gain, corresponding to 393% quantum efficiency. Responsivities of 0.13 A/W and 0.07mA/W were achieved for 1060 and 1310 nm with SiGe absorption. With V/sub ce/=2 V, we measure a -3-dB bandwidth of up to 5.3 GHz for phototransistors with a 4-/spl mu/m/sup 2/ active area and 2.0 GHz for phototransistors with 60-/spl mu/m/sup 2/ active area and finger contacts. This high-efficiency and high-speed phototransistor is an enabling device for monolithic receiver integration.     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs     

Self-consistent transit-time model for a resonant tunnel diode

We present a self-consistent compact model for the small-signal impedance of a resonant tunnel diode (RTD) with a finite collector transit time. The effect of the collector transit time on the device impedance is described for three In/sub 0.53/Ga/sub 0.47/AsAlAs-InAs RTDs with current densities ranging from 14 kA/cm/sup 2/ to 570 kA/cm/sup 2/ with various collector spacer lengths for dc biasing in both the positive and negative differential resistance regions.     

Printed microinductors on flexible substrates for power applications

A low-profile microinductor was fabricated on a copper-clad polyimide substrate where the current carrying coils were patterned from the existing metallization layer and the magnetic core was printed using a magnetic ceramic-polymer composite material. Highly loaded ferrite-polymer composite materials were formulated, yielding adherent films with 4/spl pi/M/sub s//spl ap/3900 G at +5000 Oe applied DC field. These composite magnetic films combine many of the superior properties of high temperature ceramic magnetic materials with the inherent processibility of polymer thick films. Processing temperatures for the printed films were between 100/spl deg/C and 130/spl deg/C, facilitating integration with a wide range of substrates and components. The quality factor of the microinductor was found to peak at Q=18.5 near 10 MHz, within the optimal frequency range for power applications. A flat, nearly frequency independent inductance of 1.33 /spl mu/H was measured throughout this frequency range for a 5 mm/spl times/5 mm component, with a DC resistance of 2.6 /spl Omega/ and a resonant frequency of 124 MHz. The combination of printed ceramic composites with organic/polymer substrates enables new methods for embedding passive components and ultimately the integration of high Q inductors with standard integrated circuits for low profile power electronics.     

Output interface with latching driver for LTS-SFQ circuits

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J/sub c/ of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J/sub c/ of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO/sub x/-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J/sub c/ of 45 kA/cm/sup 2/, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa/sub 2/Cu/sub 3/O/sub 7-x/ have an optimum J/sub c/ of 60 kA/cm/sup 2/ that gives the smallest punchthrough probability lower than 10/sup -15/ for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J/sub c/ of 45 kA/cm/sup 2/ for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J/sub c/ is important to prepare 40-Gb/s SFQ systems. The J/sub c/ of 60 kA/cm/sup 2/ is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.     

High-efficiency enhancement-mode power heterojunction FET with buried p/sup +/-GaAs gate structure for low-voltage-operated mobile applications

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p/sup +/-n junction gate structure for low-voltage-operated mobile applications. The buried p/sup +/-GaAs gate structure effectively reduced on-resistance (R/sub on/) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p/sup +/-gate HJFET exhibited a low R/sub on/ of 1.4 /spl Omega//spl middot/mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.     

Micropositioning device using impact force of piezoelectric flying wires

In this paper, a micropositioning device for precision positioning of miniaturized parts is proposed. This device uses piezoelectric flying wires to generate impact forces for actuating a target object to be positioned. The proposed device features two main characteristics: the impact force can actuate a half-tightened object with a high degree of precision, and the thin flying wire is suitable for the actuation of miniaturized object. Fundamental properties of the proposed device were examined experimentally and theoretically based on a basic positioning unit. Furthermore, for the practical application in assembly works, the control system for a three degrees-of-freedom micropositioning device with positioning range of (/spl plusmn/250 /spl mu/m, /spl plusmn/250 /spl mu/m, /spl plusmn/30 mrad) along the X-, Y-, and /spl Theta//sub z/-axes was implemented. The target object (16/spl times/24/spl times/6 mm) was successfully positioned with positioning accuracies of (/spl plusmn/1 /spl mu/m, /spl plusmn/1 /spl mu/m, /spl plusmn/0.2 mrad), based on a derived heuristic control model.     

VMOS technology applied to dynamic RAMs

A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 /spl mu/m photolithography, one-transistor cells with a cell size of 150 /spl mu/m/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 /spl mu/m design rules.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

RF transmission over multimode fibers using VCSELs-comparing standard and high-bandwidth multimode fibers

Fiber-optic radio-frequency links have been assembled using oxide-confined vertical-cavity surface-emitting lasers (VCSELs) and multimode fibers. Links with single and multimode VCSELs and with standard and high-bandwidth fibers have been evaluated and compared in the frequency range of 0.1-10 GHz. The best results were obtained for links with a multimode VCSEL and a high-bandwidth fiber. For a 500-m-long link, a spurious free dynamic range of 104 dB/spl middot/Hz/sup 2/3/ at 2 GHz and 100 dB/spl middot/Hz/sup 2/3/ at 5 GHz were obtained while allowing for a VCSEL-fiber misalignment of /spl plusmn/12 /spl mu/m. Corresponding numbers for the intrinsic link gain and noise figure are -29 and -33 dB, and 39 and 42 dB at 2 and 5 GHz, respectively. Inferior performance was observed for the standard fiber link due to a larger variation in modal group velocities. This paper also presents a detailed link analysis to identify performance limitations and to suggest modifications for improved performance.     

Analysis of mode quality factors and mode reflectivities for nanowire cavity by FDTD technique

The mode frequency and the quality factor of nanowire cavities are calculated from the intensity spectrum obtained by the finite-difference time-domain (FDTD) technique and the Pade/spl acute/ approximation. In a free-standing nanowire cavity with dielectric constant /spl epsiv/=6.0 and a length of 5 /spl mu/m, quality factors of 130, 159, and 151 are obtained for the HE/sub 11/ modes with a wavelength around 375 nm, at cavity radius of 60, 75, and 90 nm, respectively. The corresponding quality factors reduce to 78, 94, and 86 for a nanowire cavity standing on a sapphire substrate with a refractive index of 1.8. The mode quality factors are also calculated for the TE/sub 01/ and TM/sub 01/ modes, and the mode reflectivities are calculated from the mode quality factors.     

An optically-coupled crosspoint array with high dv/dt capability and high gate sensitivity

A 2/spl times/4 optically-coupled economical crosspoint array for the telephone speech path with a high breakover voltage (>450 V), high dv/dt capability (>200 V/0.1 /spl mu/s), and high gate sensitivity (<5 mA) is described. This has been achieved by a new device structure with a double-gate MOSFET and RC discharge circuitry formed on a p-n-p-n element. This MOS associated circuitry for dv/dt improvement is referred to as `MAC' p-n-p-n elements with MAC can be separated from each other with a new simple isolation technique called `canal isolation' which facilitates low manufacturing cost. Both p-n-p-n elements and LEDs are bonded face-down on a 44 pin chip carrier ceramic package with bump electrodes which again allows low manufacturing cost. The MAC enables independent control of the dv/dt capability and the gate sensitivity. The authors show the MAC performance in dv/dt improvement and various evaluations of MAC, including computer simulation. High breakover voltage technology and some processes for forming the gate-to-cathode resistor R/SUB GK/ for devices with MAC are discussed. This new optically-coupled crosspoint array with MAC makes possible a high-performance direct interface with conventional telephone sets.     

Improved coding techniques for preceded partial-response channels

A coset of a convolutional code may be used to generate a zero-run length limited trellis code for a 1-D partial-response channel. The free squared Euclidean distance, d_free², at the channel output is lower bounded by the free Hamming distance of the convolutional code. The lower bound suggests the use of a convolutional code with maximal free Hamming distance, d_max(R,N), for given rate R and number of decoder states N. In this paper we present cosets of convolutional codes that generate trellis codes with d_free ²>d_max(R,N) for rates 1/5⩽R⩽7/9 and (d _free²=d_max(R,N) for R=13/16,29/32,61/64, The tabulated convolutional codes with R⩽7/9 were not optimized for Hamming distance. Instead, a computer search was used to determine cosets of convolutional codes that exploit the memory of the 1-D channel to increase d_free² at the channel output. The search was limited by only considering cosets with certain structural properties. The R⩾13/16 codes were obtained using a new construction technique for convolutional codes with free Hamming distance 4. Newly developed bounds on the maximum zero-run lengths of cosets were used to ensure a short maximum run length at the 1-D channel output     

Piezoelectric micro-power generation interface circuits

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-/spl mu/m CMOS process is 88% and the output power exceeds 2.5 /spl mu/W with a 100-k/spl Omega/, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-/spl mu/m CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-k/spl Omega/ load and supplies a peak output power of 16 /spl mu/W with a 68-k/spl Omega/ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with an 82-k/spl Omega/ load, and also exhibits a higher peak power of 22 /spl mu/W with a 68-k/spl Omega/ load which is 37% higher than the passive full-wave rectifier.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

Performance limits of Reed-Solomon coded CDMA with orthogonalsignaling in a Rayleigh-fading channel

The asymptotic performance of Reed-Solomon (RS)-coded M-ary orthogonal signaling with ratio-threshold test (RTT) type demodulation in a Rayleigh-fading channel is considered. We show that the minimum E¯_b/N₀ needed for error-free communication is eln2 (2.75 dB) with RTT, and 4.79 (6.8 dB) with hard decisions. The optimum code rate that minimizes the required E¯_b/N₀ is e^-1 with RTT and 0.46 with hard decision, and the optimum ratio threshold approaches 1 for large M. Next, we investigate the fundamental limit in a direct-sequence spread-spectrum multiple-access (DS/SSMA) system employing an M-ary orthogonal code of length N=Mm, which is obtained by spreading every row of an M×M Hadamard matrix with a user-specific random sequence of length N. We derive the minimum E¯_b/N₀ for error-free communication as a function of the number of users, the optimum code rate that minimizes E¯_B/N₀, and the maximum limit on the total information transmission rate. Then, we consider a multirate DS/SSMA system, where a population of users simultaneously transmit at different power levels a variety of traffic types of different information rates. We derive the minimum required E¯_B/n₀ and the optimum code rate for each traffic type     

High-performance three-layer 1.3-/spl mu/m InAs-GaAs quantum-dot lasers with very low continuous-wave room-temperature threshold currents

The combination of high-growth-temperature GaAs spacer layers and high-reflectivity (HR)-coated facets has been utilized to obtain low threshold currents and threshold current densities for 1.3-/spl mu/m multilayer InAs-GaAs quantum-dot lasers. A very low continuous-wave (CW) room-temperature threshold current of 1.5 mA and a threshold current density of 18.8 A/cm/sup 2/ are achieved for a three-layer device with a 1-mm HR/HR cavity. For a 2-mm cavity, the CW threshold current density is as low as 17 A/cm/sup 2/ for an HR/HR device. An output power as high as 100 mW is obtained for a device with HR/cleaved facets.     

Compact NMOS building blocks and a methodology for dedicated digital filter applications

Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.     

Magnetics on silicon: an enabling technology for power supply on chip

Data from the ITRS2003 roadmap for 2010 predicts voltages for microprocessors in hand-held electronics will decrease to 0.8V with current and power increasing to 4A and 3W, respectively. Consequently, low power converters will move to multimegahertz frequencies with a resulting reduction in capacitor and inductor values by factors of 5 and 20, respectively. Values required at 10 MHz, for a low power buck converter, are estimated at 130 nH and 0.6 uF, compatible with the integration of magnetics onto silicon and the concept of power supply-on-chip (PSOC). A review of magnetics-on-silicon shows that inductance values of 20 to 40nH/mm/sup 2/ can be achieved for winding resistances less than 1/spl Omega/. A 1-/spl mu/H inductance can be achieved at 5 MHz with dc resistance of 1/spl Omega/ and a Q of four. Thin film magnetic materials, compatible with semiconductor processing, offer power loss density that is lower than ferrite by a factor of 5 at 10 MHz. Other data reported includes, lowest dc resistance values of 120 m/spl Omega/ for an inductance of 120 nH; highest Q of 15 for an inductance of 350 nH and a current of 1 A for a 1- /spl mu/H inductor. Future technology challenges include reducing losses using high resistivity, laminated magnetic materials, and increasing current carrying capability using high aspect-ratio, electroplated copper conductors. Compatible technologies are available in the power switch, control, and packaging space. Integrated capacitor technology is still a long-term challenge with maximum reported values of 400 nF/cm/sup 2/.