GaN基功率型LED芯片散热性能测试与分析

与正装LED相比,倒装焊芯片技术在功率型LED的散热方面具有潜在的优势.对各种正装和倒装焊功率型LED芯片的表面温度分布进行了直接测试,对其散热性能进行了分析.研究表明,焊接层的材料、焊接接触面的面积和焊接层的质量是制约倒装焊LED芯片散热能力的主要因素;而对于正装LED芯片,由于工艺简单,减少了中间热沉,通过结构的优化,工艺的改进,完全可以达到与倒装焊LED芯片相同的散热能力.     

塑封倒装焊器件DPA试验流程研究

倒装焊器件与常规的引线键合结构不同,现行的DPA标准不能完全适用于倒装焊结构.结合现有标准和倒装焊器件结构特点,以某塑封倒装焊集成电路器件为例,提出一套经过试验验证的、实用性强的倒装焊器件DPA试验流程.在原来标准的基础上提出了对BGA焊球材料成分分析、底充胶检查的超声扫描要求、芯片凸点结构检查等一些新的DPA要求.BGA焊球材料成分分析是使用能谱分析实现的,而芯片凸点结构检查则是通过对器件进行研磨开封实现的.经过试验验证,该流程方案可用于倒装焊集成电路器件的实际DPA工作.     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

高加速应力试验用于倒装焊领域

倒装焊技术已被广泛地用于电子领域.对倒装焊而言,其焊点的可靠性、密封填充物与芯片或基板间的分层一直是特别重要的课题.介绍了一种加速环境试验--HAST,用于快速评价倒装焊接在FR-4基板上面阵列分布焊点的可靠性,试验结果说明HAST能够作为一个有效的可靠性试验评价工具用于倒装焊技术领域.     

MCM—C倒装焊工艺技术研究

简要介绍了主要倒装焊技术，重点研究了实用性强、可行性好的超声热压倒装焊、导电环氧粘接倒装、ACA粘接倒装以及MCM—C基板上的芯片倒装焊区制作、倒装后芯片的下填充等工艺技术，总结了芯片倒装互连质量的主要检验要求。     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

基于主动红外的倒装芯片缺陷检测研究

传统的倒装芯片无损检测技术并不能完全满足倒装焊检测需要,为此提出了一种基于主动红外的倒装芯片缺陷检测方法。通过非接触方式对倒装芯片施加热激励,并结合红外测温设备检测芯片温度分布情况,从而对芯片内部缺陷进行诊断与识别。实验研究表明,该方法能较好地检测出倒装焊点缺陷,可应用于倒装焊芯片的缺陷检测与诊断研究。     

倒装焊对探测器频响特性影响的理论分析及工艺优化

针对光探测器在倒装焊过程中频响性能恶化的问题,建立等效电路模型分析出其原因,并通过优化倒装焊工艺条件予以有效解决。该电路模型包括探测器芯片、过渡热沉和倒装焊环节三个部分。基于倒装焊后探测器的S11参数和频响曲线提取出倒装焊环节特征参数,确认焊点接触电阻过大是引起探测器频响下降的主要原因。通过优化倒装焊工艺条件,有效减小了焊点接触电阻,基本消除了倒装焊对探测器频响特性的影响。     

基于倒装焊芯片的功率型LED热特性分析

对LED的导散热理论进行了研究,推导出了倒装焊LED芯片结温与封装材料热传导系数之间的关系。通过分析倒装焊LED的焊球材料、衬底粘结材料和芯片内部热沉材料对芯片结温的影响,表明衬底粘结材料对LED的结温影响最大,并且封装材料热传导系数的变化率与封装结构的传热厚度成反比,与传热面积成正比。该研究为倒装焊LED封装结构和材料的设计提供了理论支持。     

倒装芯片及封装技术

介绍了倒装芯片的发展过程，其中主要对制造技术、封装方法及倒装焊焊点的可靠性进行了评述。     

Interconnection Technology Based on InSn Solder for Flexible Display Applications

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip‐chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.     

采用底部填料预涂工艺的Au-Sn粘结倒芯片COF技术

概述了COF粘结技术以及应用底部填料预涂工艺的Au-Sn粘结倒芯片COF技术。     

Fine‐Pitch Solder on Pad Process for Microbump Interconnection

A cost‐effective and simple solder on pad (SoP) process is proposed for a fine‐pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60‐μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine‐pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine‐pitch SoP process and evaluate the fine‐pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45‐μm diameter and 60‐μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine‐pitch SoP and microbump interconnection using a screen printing process.     

倒装焊技术及应用

随着集成电路封装密度的提高,传统引线键合技术已经无法满足要求,倒装焊技术的发展能够解决该问题,并且得到了广泛的应用。文章介绍了倒装焊中的4种关键工艺技术,即UBM制备技术、凸点制备方法、倒装和下填充技术。其中凸点制备技术直接决定着倒装焊技术的好坏,为满足不同产品的需求,出现了不同的凸点制备技术,使倒装焊技术具备了好的发展前景。文章对各工艺技术的应用特点进行了阐述,并对倒装焊技术的发展前景进行了展望。     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

倒装芯片下填充工艺的新进展（二）

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

倒装芯片下填充工艺的新进展（一）

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses