Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

Effects of AC hot carrier stress on n- and p-MOSFET's withoxynitride gate dielectrics

Effects of AC hot carrier stress on n- and p-MOSFET's with pure, NH₃-nitrided (RTN) and reoxidized nitrided (RTN/RTO) gate oxides are studied. Irrespective of the gate dielectric used, n-MOSFET's show enhanced degradation but p-MOSFET's show suppressed degradation under AC stress as compared to DC stress for the same duration. Dependence of degradation on frequency and duty cycle of gate pulse is studied. Results show that the degradation under AC stress in n-MOSFET's is suppressed whereas it is increased slightly in p-MOSFET's with the use of RTN/RTO gate oxides instead of conventional gate oxides     

Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

Reliability of in-situ rapid thermal gate dielectrics in deepsubmicrometer MOSFET's

Several in-situ, rapid thermal gate dielectrics, 6.5-nm thick, including RTO, RTCVD, and RPECVD were used to fabricate fully implanted 0.25-μm NMOSFET's along with Furnace gate oxides. The device reliability was studied by both channel hot-carrier stress and Fowler-Nordheim electron injection. It was found that devices having RTO or RTCVD oxides have about the same hot-carrier resistance as Furnace ones, while RPECVD oxides, deposited directly on Si without a grown oxide interface, were more susceptible to shifts. Both RTCVD and RPECVD oxides have a lower Si-SiO₂ barrier height (2.7 eV); nevertheless, RTCVD oxides show enhanced resistance against interface-state generation, threshold voltage shifts, and charging during Fowler-Nordheim stressing     

Channel hot-carrier stressing of reoxidized nitrided silicondioxide

The mechanisms of channel hot-carrier-induced degradation in short n-channel MOSFETs with reoxidized nitrided oxide as the gate dielectric are discussed. Charge pumping measurements, supported by observations on the gate voltage dependence of degradation and the power law dependence of Δg_m on stress time, demonstrate that virtually no interface trap generation occurs in reoxidized nitrided oxides and that electron trapping is the dominant degradation mechanism. Although electron trapping can be enhanced in these dielectrics, this mechanism is not as important for device degradation as interface trap generation, and the net effect is substantially improved resistance to hot-carrier stress. A three-orders-of-magnitude improvement in device lifetime (versus conventional oxide) is demonstrated     

Reliable fluorinated thin gate oxides prepared by liquid phasedeposition following rapid thermal process

A reliable fluorinated thin gate oxide prepared by liquid phase deposition (LPD) following rapid thermal oxidation (RTO) in O₂ or nitridation (RTN) in N₂O ambient was reported. Fluorine (F) atoms incorporated into the oxides during LPD process are found to be helpful to the improvement of oxide quality. It is observed that these fluorinated gate oxides show good properties in radiation hardness, charge to breakdown (Q_bd), and oxide breakdown field (E_ox) endurances. Interestingly, the Q_bd 's for the fluorinated gate oxides are 10 times larger than those for the gate oxides prepared by RTO in O₂ or RTN in N₂ O directly. Some of the E_ox's are even higher than 17 MV/cm for the samples investigated in this work     

Hot-carrier degradation of p-MOSFET's under analog operation

The hot-carrier degradation of p-MOSFET's is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Temperature and electric field characteristics of time-dependentdielectric breakdown for silicon dioxide and reoxidized-nitrided oxides

TDDB characteristics of 150 Å reoxidized nitrided oxide (ONO) gate dielectrics were examined at temperatures from 77 K to 400 K. These ONO films were processed with different conditions of rapid thermal nitridation (RTN) and rapid thermal re-oxidation (RTO). Optimized ONO films show better Q_bd performance while maintaining a similar temperature and electric field dependence compared to SiO₂. The low temperature activation energy for ONO and SiO₂ is found to be strongly temperature dependent, and the charge to breakdown, Q_bd, is closely related to the electron trap generation/trapping rate rather than the amount of hole trapping for high field stress. To further verify the effect of hole trapping on TDDB, X-ray irradiation was applied to wafers at different process steps. The results clearly show that the amount of hole trapping does not correlate with the charge to breakdown     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Thin gate and analog capacitor dielectrics for submicron device fabrication

The miniaturization of devices in ULSI circuits are accompanied by shrinking vertical, as well as horizontal, device parameters such as junction depth, lateral impurity diffusion and film thicknesses. This is achieved by decoupling process steps,i.e. processing at a reduced thermal budget. However, as device dimensions decrease, greater demand in transistor noise immunity and reliability may not be achievable with low-temperature (<900° C) oxidation processes. Low temperature CVD ONO (oxide-nitride-oxide) dielectrics have been evaluated for applications in ULSI gate as well as capacitor structures. Time dependent dielectric breakdown data have shown that ONO has longer lifetime than thermal oxide of equivalent thickness. Such stacked dielectrics nevertheless result in complex processing steps. With the advances in rapid thermal processing equipment today, rapid thermal oxide (RTO) has been shown to offer potential benefits of high temperature without significant addition to the overall thermal budget. We have shown that transistors with RTO gate oxides exhibit longer lifetime and lower noise compared to those with furnace grown gate oxides. We have also shown that interpoly RTO oxides have remarkable dielectric strength of >8 MV/cm. For enhanced radiation hardness and impurity masking capability as well as higher permittivity, rapid thermal nitrided oxides may be a potential choice deserving further evaluation. These nitrided oxides must be reoxidized to reduce densities of interface states and electron traps created during the nitridation process.     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.     

Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics

Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate exponentially dependent on the instantaneous stress voltage and oxide thickness. This is contrary to conventional wisdom that maintains that HBD is a fast thermally driven process. The HBD degradation rate (DR) for a 15 /spl Aring/ oxide scales from >1 mA/s at 4 V to <1 nA/s at 2 V, extrapolating to <10 fA/s at use voltage. Adding the HBD evolution time to the standard time-to-breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude.     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

Improved hot-carrier immunity in CMOS analog device with N2O-nitrided gate oxides

The authors report on the hot-carrier effects on analog device performance parameters in CMOS devices with N₂O-nitrided gate oxides. The hot-carrier-induced degradation has been studied in terms of drain output resistance, voltage gain, differential offset voltage, and voltage swings. Results show that, N₂O nitridation significantly improves the hot-carrier immunity in these aspects, especially for n-channel MOSFETs. Analog and digital device performance degradations have been compared     

Improved analog hot-carrier immunity for CMOS mixed-signalapplications with LATID technology

This paper reports the results of an investigation of hot-carrier effects on analog performance in LATID (Large-Angle-Tilt-Implanted-Drain) and conventional LDD submicron CMOS technology. The investigation focuses on hot-carrier induced degradation of voltage gain, degradation of drain output resistance, and drift of offset voltage of differential pairs. Results illustrate that LATID technology significantly out-performs LDD technology in regard to hot-carrier immunity of key analog parameters in short channel length devices as well as in relatively long channel length devices. The improvement of analog hot-carrier immunity with LATID is attributed to the mechanisms of reduction and departure of high electrical field from the drain area. Results suggest that LATID technology is a promising candidate for mixed-signal ULSI applications     

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO₂ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO₂ dielectrics to thin stacked gate dielectrics are discussed