Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

Frequency compensation of a multistage operational amplifier (op‐amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op‐amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two‐stage and three‐stage op‐amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well‐known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed‐loop poles and zeros of the op‐amp. Intuitive graphical design procedures for two‐stage and three‐stage op‐amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three‐stage op‐amp in a standard 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. With a load capacitance of 500 pF, post‐layout simulations show that the op‐amp achieves a low‐frequency gain of 144 dB, a phase margin of 58^°, and a unity‐gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8‐V supply voltage. Comparisons with the published amplifiers show that our op‐amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.6 V, 2.11 MHz, 62 dB SFDR active‐RC filter in 0.13µm CMOS process

Active‐RC biquad is proposed, which allows the DC level of the input of operational amplifier (op‐amp) to be different from that of the op‐amp output, enabling the low‐voltage operation. The proposed biquad realizes a second‐order transfer function with only one op‐amp, rendering even lower power consumption. By cascading two biquads, a 0.6 V fourth‐order filter is realized in a 0.13µm CMOS technology. While dissipating only 0.42 mW, the filter shows 2.11 MHz cut‐off frequency and 62 dB spurious‐free dynamic range. Copyright © 2008 John Wiley & Sons, Ltd.     

大功率半导体激光器脉冲式恒流驱动电路设计

针对半导体激光器驱动电路的脉冲式恒流需要,提出了一种以金属氧化物半导体场效应晶体为开关器件,采用了闭环反馈系统,运用负反馈原理输出恒定电流的半导体激光器驱动电路。为了防止过冲电压和纹波造成半导体激光器的损坏,在电路的设计中加入了限流保护电路并且使用了高摆率的运放。经测试,消除了过冲电压,实现了脉冲恒流的输出,实际应用表明该脉冲恒流源驱动电路对激光器安全可靠,峰值功率可达40 W。     

Efficient power‐bus modeling based on an adaptive frequency sampling technique

This paper presents an adaptive frequency sampling algorithm to generate a rational macromodel of a power delivery network. To this aim, the cavity model is assumed to represent the structure and accurate models of conductor and dielectric losses are incorporated. The adaptive sampling algorithm allows one to minimize the order of the macromodel and number of frequency samples used to extract the rational macromodel. The numerical results demonstrate the effectiveness of the proposed method. Copyright © 2008 John Wiley & Sons, Ltd.     

Analysis and design of voltage‐controlled current sources for a grounded load

The paper presents the structure and the principle of operation of the ‘improved’ Howland current pumps (or voltage‐controlled current sources (VCCSs) for a grounded load). In particular, under review is the VCCS employing power operational amplifier (op amp) and the VCCS using low power op amp and an additional power transistor, extending working dynamic range. On the basis of analysis of the operational principle, the equations for transfer functions of both circuits and formulas for the related dynamic electrical parameters are obtained. Moreover, using these formulas, a design procedure is developed, and recommendations for simulation modelling are given. The efficiency of the proposed procedure is verified by simulation modelling and experimental testing of sample electronic circuits of VCCSs. Copyright © 2013 John Wiley & Sons, Ltd.     

Reconciling Spice results and hand calculations: unexpectedproblems

In an earlier paper, the authors analyzed and offered solutions to several discrepancies that often arise when electronic engineering students seek to understand and reconcile their hand calculations with Spice simulation results. This paper presents several additional commonly encountered, but quite unexpected, problems that frustrate and confuse students. In particular, the authors discuss the difficulties that arise from the use of Miller compensation in the middle gain stage of a typical bipolar op amp, the discrepancies that occur when a transistor is operating in “high level injection region”, the techniques for minimizing the voltage offsets when the input transistors match perfectly and the difficulties in calculating common mode rejection ratio caused by the difference between the AC and DC gains of current mirrors     

Adaptive switched capacitor biquadratic filter with high-frequency applications

This paper considers the design of an adaptive biquadratic switched capacitor (SC) filter. It uses a low-sensitivity SC integrator, a gain stage and four-quadrant analogue multipliers (4-QAMs). The resulting circuit exhibits reduced sensitivity to op amp non-idealities (DC offset, finite op amp gain and bandwidth) associated with analogue adaptive filters. The techniques used are specific to high-precision and high-frequency operation. Test results obtained from a prototype circuit verify the viability of the proposed architecture.     

Novel non‐linear macromodel suitable for SPICE simulation of analogue multipliers realized with bipolar and CMOS technologies

The purpose of this paper is to propose a simple and accurate non‐linear macromodel for analogue multipliers. The performance of the new macromodel is demonstrated by comparing the SPICE simulation results obtained with the device‐based models and with the macromodel. The most important result obtained in the frame of this work is the combination of accurate modelling with reduced computer time, thus providing the IC designer with the possibility of speeding up the simulation of large electronic systems. Copyright © 1999 John Wiley & Sons, Ltd.     

考虑风险和收益平衡的输电断面供电方案优化

基于N-1静态安全约束校验模型的传统输电断面最大输电能力(total transfer capability,TTC)计算结果所确定的电网供电方案过于保守,为此,提出考虑供电收益和风险的电网供电方案多目标优化模型,综合考虑电网的风险、经济指标,引入风险模型和获益模型,对电网供电方案进行多目标优化,并应用多目标粒子群算法和主观权重结合熵权的余弦排序进行求解与决策。实际算例的仿真结果表明该模型和方法的有效性和可行性,技术人员可根据实际需要对方案进行分析选择。     

提高青岛电网供电可靠性的研究

简述了青岛电网现状及近几年来为提高供电可靠性所做的工作,分析了地方电厂、电气化铁路等对青岛电网的影响,对因故障引起的低电压释放负荷问题进行了探讨,提出了确保可靠供电的对策。     

特高压磁阀式可控电抗器自抗扰DSP控制系统

特高压磁阀式可控并联电抗器采用自抗扰控制离散算法可产生良好调节特性,提高特高压交流输电系统的无功平衡能力、提高电网的稳定性和供电质量。采用Matlab2008A和TMS320F28335高速浮点DSP为核心器件半实物仿真装置,对特高压输电系统进行了建模仿真和实时控制。试验结果表明,该控制算法可以适应磁阀式可控并联电抗器复杂非线性的控制特点,满足特高压线路中的无功功率高速响应要求。理论分析得到了在不同负载特性和全补偿条件下,特高压磁阀式可控电抗器的控制规律,为该装置工程设计提供了理论基础。     

基于模式切换的逆变器与发电机并联控制策略

随着新能源技术的发展,偏远山区、海岛等独立电力系统越来越多地采用新能源发电设备与柴油发电机混合供电方式。针对这类系统中新能源逆变器单独供电、与柴油发电机并联供电的功能需求,以逆变器单独供电时采用电压源控制、与柴油发电机并联时采用电流源控制为基础,提出基于逆变器控制模式切换和柴油发电机准同期并联相结合的控制策略,解决逆变器与柴油发电机并联过程的控制问题,电磁暂态时域仿真和1∶1样机物理实验验证了该控制策略的有效性。     

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

An amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than ?37 dB over the full frequency range.     

AH型断路器电子脱扣器误动作分析

针对大容量AH型断路器轻载频繁跳闸问题，对其电子脱扣器性能参数及电路原理进行了测试与分析，得出了电子脱扣器不加辅助电源是引起大容量AH型断路器误动作的根源的结论。加装了DC24V辅助电源后，AH型断路器的电子脱扣器的工作性能稳定可靠。     

Simple and accurate non-linear current conveyor macromodel suitable for simulation of active filters using CCIIs

This paper describes a simple and accurate non-linear current conveyor macromodel which is especially suitable for simulation of active filter applications. The results obtained show that the proposed macromodel approximately represents the current conveyor with the same accuracy as the semiconductor SPICE device models, but with a considerably reduced computer time. © 1998 John Wiley & Sons, Ltd.     

The electrothermal macromodel of the MA7800 monolithic positive‐voltage regulators family

This paper presents the problem of modelling the linear three‐terminal monolithic positive‐voltage regulators belonging to the MA7800 family with self‐heating taken into account. The new electrothermal compact macromodel of the considered family of devices has been proposed by the authors. This macromodel was implemented to SPICE with the use of the ABM option. The proposed macromodel was verified experimentally for the MA7805 regulator and a good agreement between the calculation and measurement results was obtained. Copyright © 2006 John Wiley & Sons, Ltd.     

用于有源电力滤波器谐波和无功电流检测的一种改进同步参考坐标法

根据通用瞬时功率理论,提出了一种电源电压矢量同步参考坐标变换的有源滤波器无功和谐波电流检测方法.该方法通过对电源电压矢量的同步旋转跟踪,实现对谐波和无功电流的检测,省去了锁相环及三角函数计算,计算方法简单.仿真和实验结果证实了采用本检测方法得到的补偿电流具有很好的补偿性能,而且既可适用于三相对称正弦电源系统,也可适用于不对称非正弦电源系统.     

High frequency active-R filters

Limitations on active-R filter pole displacements are studied. the maximum magnitude of the natural frequencies is presented as a function of the op. amp. GB. Structures to realized biqads with two op. amps. and a predistortion technique, to take into account the amplifier's high frequency pole, are proposed. Experimental results are presented which confirm the theory.