Investigation of charge trapping and breakdown characteristics of sputtered-Y2O3 on n-GaAs substrates

Metal-oxide-semiconductor (MOS) capacitors fabricated by depositing yttrium oxide (Y₂O₃) using radio frequency sputtering system on top of n-GaAs substrates have been investigated. To study the interface properties, charge trapping behavior and breakdown characteristics of Y₂O₃ gate dielectric, the MOS capacitors were subjected to constant current stress, high pulse voltage stress and high constant voltage stress. The average value of the cross section of generated traps during electrical stress has been determined from our experimental data. Further the trap charge density, its distribution and location have been investigated by measurements on application and subsequent withdrawal of high pulse voltage stress. Additionally, stress induced leakage current density and time dependent dielectric breakdown characteristics have been obtained and time-to-breakdown exceeding 840 s is observed for Y₂O₃ gate dielectrics directly deposited on n-GaAs. Our experimental results have been analyzed with simple analytical formulae available in the literature.     

Electrostatic pulse breakdown in nmos devices

The electrostatic discharge (ESD) sensitivity of small dimension n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) has been investigated. NMOS FETs of varying dimensions and a constant gate oxide thickness of 400® were each subjected to a single ESD voltage pulse of between 50 and 250V at temperatures between 25 and 200°C. Over 4000 devices were used, all resident on a single 3 inch silicon wafer. The object of the experiment was to determine the dependence of device ESD sensitivity on temperature, voltage and device dimensions as well as to investigate the mechanisms that cause oxide breakdown as a result of ESD damage. No temperature dependence of device ESD sensitivity was observed within the range of the experiment. A significant voltage dependence was observed, with degradation accounting for over 80 per cent of devices at 250V. A cumulative ESD effect was observed, whereby the degradation of device performance was found to increase with the number of applied pulses. Analysis of the breakdown characteristics revealed that the cause of damage was oxide breakdown. Application of the ESD pulse appears to lead to oxide breakdown through impact ionization within the oxide, the very short duration of the pulse not being favourable to processes involving electron trapping unless these traps are already present in the oxide.     

Effect of nitrogen incorporation to oxidation process on the reliability of magnetic tunnel junctions

Magnetic tunnel junctions (MTJs) were fabricated using nitrogen-mixed oxygen plasma (O/sub 2/:N/sub 2/=10:1). From the measurements of time-dependent dielectric breakdown (TDDB) under a constant voltage stress, the reliability of MTJs with an oxy-nitride barrier was investigated and compared with that of MTJs fabricated using pure oxygen plasma. The reliability of MTJs with an oxy-nitride barrier is much improved with the incorporation of nitrogen to oxidation process. In addition, the reliability of the oxy-nitride barrier is gradually enhanced with increasing oxy-nitridation time even after the time exceeds the optimal value. It is believed that the enhancement is due to the bonding of nitrogen to electron traps both in the oxide barriers and at the bottom interface. The characteristics of the bonding were examined by XPS measurements, which reveal a nitrogen 1s peak in Al-N bond. The lifetime of the two barriers was also estimated for comparison.     

电应力对HfO2栅介质漏电流的影响

使用导电原子力显微镜（Conductive Atomic Force Microscopy,CAFM）对电压应力作用下HfO2栅介质薄膜局域漏电点的形成和产生机制进行了研究,结果表明,在电压应力作用下,HfO2介质层中的缺陷被驱动和聚集形成导电通道,产生漏电点。漏电点产生的数量、漏电流大小均受电压应力和作用时间的影响。HfO2栅介质层中晶界处的缺陷密度高于晶粒处,导致晶界处更容易产生漏电通道。在栅介质击穿过程中,电压应力在诱发漏电流产生的同时产生焦耳热,对HfO2介质表面造成热损伤,导致击穿后HfO2介质表面出现凹陷。     

A real-time C-V measurement circuit for MOScapacitors under current stressing

A real-time C-V measurement circuit for MOS capacitors which are under constant current stress is presented. For this system, the MOS device is kept current-stressed and its stressed C-V characteristics can be measured instantaneously when desired. The charge filling information on oxide traps and surface states can be obtained in real time during the stressing process, even to the point of capacitor breakdown. With this circuit it has been shown that, for an Al-gate MOS structure, charges on traps and interface surface states recover immediately after the stressing is removed. It is demonstrated that the breakdown of the oxide is a sudden phenomenon, and is caused mainly by charge trapping in the oxide     

Analysis of gate oxide damage by ultraviolet light during oxide deposition in high density plasma

The UV-induced damages to the gate oxide in a commercially available high-density-plasma dielectric oxide deposition system for the ultra-large integrated circuit fabrication process were analyzed systematically using the metal-oxide-semiconductor capacitors with different antenna ratio. UV-induced damages exclusively in the gate oxide were evaluated by depositing 2500 Å thick oxide layer only once and twice on the two wafers separately and comparing the two results: the deposition of the oxide layer of only 2500 Å did not cause any degradation in the SPDM wafer while the double deposition revealed antenna-ratio dependent shift of the breakdown voltage. The deviation of the values of breakdown voltage of the damaged wafer from its normal ones was found mainly at the center of the wafer where the intensity of the UV light is generally higher in the inductively coupled plasma source.     

Stability of pentacene organic field effect transistors with a low-k polymer/high-k oxide two-layer gate dielectric

This paper reports on the processing and the characterization of pentacene organic field effect transistors (OFETs) with a two-layer gate dielectric consisting of a polymer (PMMA) on a high-k oxide (Ta₂O₅). This dielectric stack has been designed in view to combine low voltage operating devices, by the use of a high-k oxide which increases the charge in the accumulation channel and the gate capacitance, and highly stable devices which generally could be achieved with polymer dielectrics but not necessarily with strongly polar high-k oxides. Bi-layer dielectric devices were compared to those with only Ta₂O₅ or PMMA gate insulators. Bias stress at room temperature was used to assess the electrical stability. A very low operating voltage was achieved with Ta₂O₅ but these devices exhibit hysteresis and degraded characteristics upon bias stress. OFETs with PMMA revealed very stable but operate at rather a high voltage due to the low dielectric constant of PMMA. Reasonably stable devices operating at about 10 V could have been obtained with PMMA/Ta₂O₅ two-layer dielectric. The origin of observed threshold voltage shift and mobility decrease upon bias stress are discussed.     

Label-free DNA detection with a nanogap embedded complementary metal oxide semiconductor

A nanogap embedded complementary metal oxide semiconductor (NeCMOS) is demonstrated as a proof-of-concept for label-free detection of DNA sequence. When a partially carved nanogap between a gate and a silicon channel is filled with charged biomolecules, the gate dielectric constant and charges are changed. When the gate oxide thickness reduces, the threshold voltage is significantly affected by a change of the charges, whereas it is scarcely influenced by a change of the dielectric constant. In the case of DNA, those two factors act on the threshold voltage oppositely in an n-channel NeCMOS but collaboratively in a p-channel NeCMOS because of the negative charges of DNA. Hence, a p-channel NeCMOS with a thin gate oxide is more attractive for DNA detection because it enhances the shift of threshold voltage; that is, it improves the sensitivity of DNA detection. In addition, the shift of threshold voltage according to the nanogap length is also investigated and the longer nanogap shows more shift of the threshold voltage.     

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO_x) dielectric layer, deposited with different oxygen partial pressure (30, 35 and 40%) and annealed at 550, 750 and 1000 °C, were fabricated and characterized.Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO_x films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of − 1 V, as low as 1 nA/cm² for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers.     

Pb掺杂SnO2压敏电阻的晶粒尺寸效应

研究了Pb3O4对(Co，Nb)掺杂SnO2压敏材料电学性质的影响，当Pb3O4的含量从0．00增加到0．75％(摩尔分数，下同)时，(Co，Nb)掺杂SnO2压敏电阻的击穿电压从426V／mm迅速减小到160V／mm，40Hz时的相对介电常数从1240迅速增加到2760，这说明Pb3O4是调控SnO2压敏材料击穿电压和介电常数的敏感添加剂，晶界势垒高度测量表明，在实验范围内Pb的含量对势垒高度的影响很小，随着Pb含量的增加，SnO2的晶粒尺寸的迅速长大是击穿电压迅速减小和介电常数迅速增大的主要原因，对样品的复阻抗进行了测量，发现未掺杂Pb的样品具有最低的晶界电阻，而掺杂0．50％Pb3O4的样品具有最高的晶界电阻，提出了一个修正的缺陷势垒模型，指出了替代Sn的受主不应当处于晶界上，而应处于耗尽层的Sn的晶格位置。     

Influence of gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors

In this article, the significant effect of a thin gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors (DCFETs) is first demonstrated. When compared to the conventional InGaP/InGaAs DCFET, the device with the gate thermal oxide layer exhibits a higher gate turn-on voltage and nearly voltage-independent transconductances as the gate-to-source is biased form −0.75 V to 0 V, while the maximum transconductance is lower. Experimentally, the transconductance within 90% of its maximum value for gate voltage swing is 1.63 V in the gate-oxide device, which is greater than that of 1.35 V in the device without the gate thermal oxide layer. Furthermore, it maintains a high drain current level at negative gate bias in the gate-oxide device, which can be attributed that the thermal oxide layer with a considerably large energy gap absorbs more of gate negative voltage and the influence of negative voltage on the gate depleted thickness is relatively slight.     

Turn-off current variation in drain-offset polysilicon thin film transistors

Bottom gate drain-offset polysilicon thin film transistors (poly-Si TFTs) were fabricated on SiO₂ coated Si wafers. After completing gate oxide deposition, we exposed the wafers to air in a clean room. Poly-Si films were deposited on the gate oxides for the active layer of the drain offset poly-Si TFTs with changing the air-exposure time. Threshold voltage shift to positive value and turn-off current raise with increasing the air-exposure time were observed. In this paper, we focused on evaluating the causes of the turn-off current raise with the air-exposure time. The carbons piled up at the poly-Si/SiO₂ interface were observed by a SIMS measurement, which is considered to be the origin of negative charges. The concentration of the carbon was remarkably increased by expanding the air-exposure time. The existence of the negative charges in the oxide was also found by a capacitance-voltage measurement. We conclude that the carbons originated from the air in the clean room are the main cause of the threshold voltage and turn-off current variation in the drain-offset poly-Si TFTs.     

Investigations on Al/BaTiO3/GaN MFS structures

A metal–insulator–semiconductor (MIS) device structure has been established on GaN by using BaTiO₃, a ferroelectric material, as an insulating layer. The composition of the deposited ferroelectric layers was studied using X-ray photoelectron spectroscopy (XPS) and energy-dispersive X-ray (EDX) analysis. Fabricated Al/BaTiO₃/GaN metal–ferroelectric–semiconductor (MFS) structures have been characterised through capacitance–voltage (C–V) measurements. Improved C–V characteristics have been observed in comparison to other traditional oxide insulators. An inversion of GaN MFS structures has been attained just for the applied voltage of 5 V due to the high dielectric constant and large polarisation field of the gate ferroelectric layer. The bias stress measurements indicate a high stability of the ferroelectric material over a period of 10⁴ s.     

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al(2)O(3) gate oxides

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8?V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.     

Study on electrical degradation of p-type low-temperature polycrystalline silicon thin film transistors with C-V measurement analysis

Laser recrystallized low-temperature poly-silicon (LTPS) films have attracted attention for their application in thin-film transistors (TFTs), which are widely used in active matrix display. However, the degradation behavior of p-type LTPS TFTs is not quite clarified yet. In this paper, the instability mechanisms of p-channel LTPS TFTs under DC bias stress have been investigated. From the IV transfer curves, it was observed that LTPS TFT's mobility increases after stress at some bias conditions. This degradation is most likely caused by interface traps between the poly-Si thin film and the gate insulator, as well as the damaged junction of the drain from stress. In this work, the assumption is examined via C-V measurement. It is found that the C_GD curves of the stressed TFT slightly increase for the gate voltage smaller than the flat band voltage V_FB. However, the C_GS curves of the stressed device are almost the same as those before stress. By employing simulation, it is found that the degradation of p-type TFTs under this stress condition is mainly caused by the trapped charges at the interface between the gate and the drain region, which is generated by the high voltage difference applied during DC bias stress.     

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.     

A statistical model for step and ramp voltage breakdown tests in thin insulators

A spread is observed in times to breakdown when step or ramp voltage tests are applied to thin film insulators which have non-shorting breakdowns and which are cleared of weak spots. Following earlier work on sequences of breakdowns in liquids, we investigated the properties of the spread of observations in thin insulators with a statistical model. Probability density functions are derived for the times to breakdown for step and ramp tests, and a relation is given for the ratio of the mean times to breakdown for ramp and step tests. The results agree with experimental observations on the oxides of aluminum and hafnium. This indicates a randomness of the breakdown process and permits the calculation of ramp breakdown voltages from the measured step breakdown voltages. Quantitative agreement is not obtained for silicon dioxide, probably owing to the lack of independence in the location of consecutive breakdown events.     

The influence of operating parameters on pulsed D.C. magnetron sputtering plasma

This paper describes the breakdown voltage characteristics in a pulsed D.C. magnetron sputtering system under varying conditions of frequency, current and pulse-off time. The behaviour of the breakdown voltage with pulsing frequency at different pressures and constant pulse-off time was recorded and revealed that the breakdown voltage decreased consistently as the frequency increased up to 70 kHz. Above this frequency, perturbation in the breakdown voltage was noted, possibly due to the rise in pre-breakdown current during the few microseconds of pulse-on time. This perturbation effect was no longer observed when the operating current was increased. The breakdown voltage was seen to decrease when the pulse-off time was increased while keeping the total period of the pulse constant.     

Anodic oxidation of tantalum in water and biological solutions using current limiting constant voltage method

A reliable method is developed for preparing tantalum pentoxide film targets in natural water and biological fluids (urine, blood plasma and serum) by the anodization of tantalum metal using a current limiting constant voltage method. Tantalum pentoxide film targets are successfully prepared at a current density of 10 mA cm⁻² at an anodic voltage ranging from 20 V to 100 V without any oxide breakdown. The results show that for the same applied voltage, more ionic concentration in biological solutions leads to a higher rate of oxide growth than in water and a darker interference color. The analysis shows that anodic oxidation is more likely to breakdown in a biological environment than in pure water for the same oxidation time and applied voltage. The oxide film capacitance is found to be only slightly dependent on pH and anodic voltage with higher capacitive films in biological solutions than for water.     

Graphene-graphite oxide field-effect transistors

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3.