Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems

This paper presents the Miriã tool that synthesizes multi-burst mode asynchronous controllers. An important feature of our solution is its capability of handling pairs of input burst that satisfy a set of properties. Such multi-burst may be formally described by two burst operators: OR and concurrence. A formal specification, which we called multi-burst graph (MBG), was developed to capture these features. The Miriã tool starts from a MBG specification producing asynchronous controllers as generalized RS architectures. This type of architecture handles efficiently edge-sensitive, non-monotonic (conditional) level sensitive, directed don’t-care and undetermined signals, which may occur when designing asynchronous circuits for heterogeneous systems. When compared to asynchronous controllers generated by the 3D tool, our experimental results frequently present a shorter cycle time, a reduced area and a faster interaction with the external environment.     

High performance asynchronous design using single-track full-buffer standard cells

This paper presents a high-performance asynchronous template, single-track full-buffer (STFB), which achieves close to full-custom performance using a standard cell design flow and industry standard CAD tools to perform schematic capture, simulation, cell layout, and automatic placement and routing. This template and flow is demonstrated and evaluated with the implementation of a 64-bit asynchronous prefix adder, and its test circuitry, using the TSMC 0.25-/spl mu/m process. The 64-bit asynchronous prefix adder layout requires 0.96 mm/sup 2/ and the entire 260-k transistor test chip reaches a measured throughput of 1.45GHz. The design demonstrates that the STFB template can yield three times higher throughput with approximately half of the area of comparable quasi-delay-insensitive (QDI) templates, requires less timing assumptions than ultra-high-speed GasP bundled-data circuits, and can be designed with an automated place and route flow.     

An asynchronous architecture for modeling intersegmental neural communication

This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented.     

Simple method of asynchronous circuits implementation in commercial FPGAs

This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require the application of additional user actions such as constraining or building hard macros. As a design example, an architecture of the asynchronous PicoBlaze compatible microcontroller and 12-bit pipelined fast array multiplier have been considered. The developed synchronous and asynchronous versions of the microcontroller as well as fast array multiplier have been implemented and tested using Xilinx FPGAs, and then compared in terms of the area requirement, power consumption and performance.     

CORBA异步消息的研究与实现

异步机制是构造大规模分布式系统必不可少的机制之一.作为一种典型的分布应用支撑平台,CORBA没有很好的解决异步机制问题,这限制了CORBA在一些领域的应用.如何在CORBA中提供异步通信支持,为上层应用提供异步通信支持成为研究的热点.本文提出一种CORBA异步消息模型Star-Async,该模型通过ReplyHandler对象实现应答处理、通过异常封装对象实现异常处理,通过基于修改抽象语法树的机制实现异步代码生成.在自主研制的分布对象中间件平台StarBus中实现了本文提出的Star-Async异步模型,实现和初步应用表明本文提出的异步消息模型为在CORBA中实现异步机制提供了一种有效的参考.     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

VTOA/VolP/N-ISDN Telephony Gateway

This article presents the architecture and implementation of a telephony gateway for interworking between N- ISDN, ATM and IP telephony. In this way, interworking is achieved both within private networks and with the PSTN, address translation being performed according to both the vtoa (atm interface) and H .323 (ip interface) specifications. The gateway implementation is based on a PC, presenting a cost- effective alternative to the equipment currently available on the market. Moreover, its highly modular software architecture allows new telephony interfaces to be easily added.     

Multistable Circuits for Analog Memories Implementation

In this work two multistable circuits suitable for analog memories implementation will be presented. These circuits have been used to implement completely asynchronous analog memories, one type based on a flash converter and thus having a linear complexity in resolution; the other based on an asynchronous successive approximation converter and thus having a logarithmic complexity in resolution.Experimental results from measurements over prototype chips will be shown and analyzed, and connections with design choiches highlighted.     

New architecture for enforcing multimedia synchronization in videoconferencing applications

This paper presents a formally defined architecture allowing the design and the corresponding implementation of a set of modules that fulfill the quality of service requirements of PNSVS (Petri Net Synchronized Videoconference System), an application designed to run on top of an asynchronous environment. It describes the mechanisms and architecture allowing the system to enforce the temporal synchronization between the audio and video streams, the presentation quality, and the end to end delay. This synchronization method relies on a formal model extending time Petri nets: the Time Stream Petri Net (TSPN) model, that will be used to completely specify the time constraints of the application streams. From this, the communication architecture is improved by introducing a new partial order transport service that maximizes the PNSVS quality of service. The partial order transport principle is presented together with the pre-synchronization sub-layer, which makes the partial order transport service match the applicative synchronization requirements. Moreover, it will be shown that each layer of this synchronization architecture can be formally modeled by a well defined set of TSPN models.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

可编程细胞神经网络硬件实现及应用研究

 本文提出一种模板可编程细胞神经网络的硬件实现方法,设计构成CNN的细胞体电路、A模板电路和B模板电路,组成CNN并进行在图像处理中的应用研究.仿真结果表明,所设计的硬件电路具有结构简单、功耗低、频率特性好、模板参数可编程等特点,可以方便地构成各种规模的CNN,在图像处理应用中具有一定的灵活性和通用性.     

An agent-based signaling architecture for supporting mobility in radio ATM networks

This paper presents a signaling architecture for supporting mobility in radio asynchronous transfer mode (ATM) networks. A new concept of mobile software agent, known as ‘representative’, is used for insulating fixed network entities from the effects of user mobility. It is shown that, depending on the physical locations of the mobile terminals, their representatives can be used for distributing the mobility management load within the fixed backbone network. This paper describes a location and a representative management scheme followed by a novel connection caching strategy which is used for implementing a family of low-latency and scalable ATM connection handovers. A prototype implementation of the proposed architecture and the associated experimental results are also presented to demonstrate the feasibility and performance of this agent-based signaling scheme. ©1997 by John Wiley & Sons, Ltd.     

Synthesis of timed asynchronous circuits

The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. Their timed circuits also tend to be more efficient, in both speed and area, compared with traditional asynchronous circuits. The synthesis procedure begins with a cyclic graph specification to which timing constraints can be added. First, the cyclic graph is unfolded into an infinite acyclic graph. Then, an analysis of two finite subgraphs of the infinite acyclic graph detects and removes redundancy in the original specification based on the given timing constraints. From this reduced specification, an implementation that is guaranteed to function correctly under the timing constraints is systematically synthesized. With practical circuit examples, it is demonstrated that the resulting timed implementation is significantly reduced in complexity compared with implementations previously derived using other methodologies     

A time-efficient architecture for multimedia applications

This paper presents an architecture that enforces time requirements and gives minimal end-to-end delays for multimedia applications. The layers and mechanisms allowing the system to fulfill the selected synchronization, i.e., the logical relationships and timed interval semantics, are presented. The proposed approach relies on the use of a formal model based on extended time Petri nets, i.e., the time stream Petri net model (TStreamPN), that allows the user to completely specify the time requirements of a given application. The architecture implements, in the application layer and on top of asynchronous environments, the requested quality of service (perceived by the user) with respect to time. At the transport layer, the use of a partial order transport service improves the reactive response of the communication transfers. Its principles are presented together with a presynchronization sublayer that makes the partial order transport service match the applicative synchronization requirements. Moreover, measurements on the implementation of a videoconference system show that the requirements of the quality of service are fulfilled     

Universal delay-insensitive systems with buffering lines

A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata.