一种超高速÷2ECL分频器

本文描述了采用氧化物隔离等平面S工艺、离子注入技术和快速热退火,以及采用电阻网络反馈信号的改进型D触发器的优化电路的设计方法研制的1500MHz÷2ECL分频器。电路在常温下的工作速度超过2000MHz,即使在85℃的高温条件下,其最高工作频率也超过1900MHz,完全满足了用户的要求。     

超高速低功耗ECL予置分频器研究

本文介绍一个÷5/6低功耗ECL予置分频器的设计,从降低电源电压,减小内部逻辑摆幅和寄生电容等几方面讨论了提高电路高速低功耗特性的途径。该电路采用串联电源电压结构,内部电路在-2.5V～-2.7V电源电压下工作。电路功耗仅为具有相同功能的普通ECL电路的1/6。采用3μm设计规则的氧化物隔离等平面S型双极工艺。发射极条实际尺寸2μm×9μm,晶体管f_i为3.2GHz。室温下典型功耗75mW,最高M作频率大于900MHz。     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

一种全新的超高速双极ECL硅工艺—氧化物隔离等平面S（Z）

氧化物隔离等平面S(z)工艺采用全离子注入工艺代替原始的扩散工艺,使得整个工艺流程更为简化,对于浅结工艺的重复性和均匀性均有较大提高。发射极条和基极条形成自对准,发射极四周靠墙。发射极条宽为3微米时,f_γ>3GHz。该工艺已应用于超高速双极ECL分频器中。     

一个ECL可预置数四位二进递减计数器的设计

本文根据用户提出的ECL可预置数四位二进递减计数器技术指标进行正向设计,确定了相应的逻辑功能,设计出了具体的计数器电路。经计算机模拟,所有结果都符合设计要求。电路采用3μm设计规则设计,用氧化物隔离等平面S型双极工艺和全离子注入技术制造。最小发射极尺寸为3μm×10μm,晶体管f_T为3.2GHz。室温下典型功耗电流90mA,最高工作频率大于400MHz。电路芯片面积1.8mm×2.9mm。     

全温超高速ECL双模预置分频器设计

本文叙述了全温(-55～+125℃)超高速ECL双模预置分频器的工作原理、电路设计、版图设计及研制结果,还简述了制作工艺。整个电路设计以提高电路工作速度和温度特性为中心,采用优化的开关电流分配、最佳的电路工作点设置、带温度补偿的电阻反馈网络结构和合理的版图设计,来提高工作速度和保证良好的温度性能。研制的÷8/9分频器,在全温范围内最高工作频率达600MHz以上。     

多晶硅发射极超高速集成电路工艺

报道了具有先进双极关键技术特征的多晶硅发射极集成电路的工艺 ,重点介绍了用难熔金属氮化物 (Zr N )作为新的刻蚀掩模实现器件的硅深槽隔离 ;E- B间自对准二氧化硅侧墙隔离 ;快速热处理实现多晶硅发射区浅结及薄基区 ;E、 B、 C区自对准钴硅化物形成 ,明显地减少串联电阻和双层金属 Al间可靠互联等先进的工艺研究 .用此套工艺技术研制出工作频率达 3.1GHz的硅微波静态分频器实验电路 ,集成度为 6 0 0门的双层金属 Al的ECL移位寄存器电路 ,最高移位频率达 45 0 MHz. 19级环振电路平均门延迟小于 5 0 ps     

简讯

我所一室在ECLⅢ系列电路制作工艺的基础上,采用先进的补偿网络设计和氧化物隔离等平面技术,于1981年10月在国内首先研制成功全温度、电压补偿的ECL100K系列五输入三门电路SF101。 该电路采用24引线双列直插式埋线陶瓷管壳封装。其典型参数与国外同类产品F100101相当:     

650MHz÷10/11预置分频器工艺研究

本文介绍了改进后的氧化物隔离等平面-I工艺在专用集成电路中的应用,采用这种工艺制作的650MHz÷10/11预置分频器通过了军用考核(-55℃～+85℃)标准,常温下最高工作频率可达740MHz。     

硅材料对双极超高速器件的影响

本文选择ECL(发射极耦合逻辑)亚毫微秒门电路EB60、ECL1000MHz÷10分频器S8665、ECL1000MHz÷2分频器S032为样品,从晶向、少子寿命、“雾”及薄外延等方面分析讨论了硅材料对双极超高速器件成品率和性能参数的影响。     

实用化28层陶瓷基板的设计与制作

针对 MCM技术发展的现状提出了采用新型技术设计制作超多层陶瓷基板的设计方法和工艺路线。介绍了多层布线软件的二次开发及制备过程中的互连孔冲制、复合孔化、高精度层压等技术 ,并对 2 5～ 45层的超多层陶瓷基板的研究结果进行了总结和应用前景展望。     

A monolithic decode-drive circuit for magnetic memories

The highly replicated decode-drive circuitry of magnetic memories is being produced at a very low cost with batch-fabricated integrated-circuit technology. This has resulted from judiciously reconfiguring traditional circuit forms in order to optimize their fabrication. A new monolithic circuit function and its application are described. The circuit is used for low-cost high-speed 400-mA switching in magnetic memories. The functions of address decoding and timing control are also incorporated into the circuit. The address scheme employs no transformers and possesses the advantages of miniaturization. Details of the circuit configuration, topology, and packaging are described and illustrated.     

高密度通孔薄膜电路工艺技术研究

通过对薄膜电路制作工艺的系统研究,提出了一种新型的制作高密度通孔薄膜电路工艺方法,克服了高密度通孔薄膜电路对溅射用金靶、喷雾式涂胶和反应离子刻蚀等工艺技术和设备的依赖,降低了高密度通孔薄膜电路研制成本.该新型工艺方法已成功应用于延时电路、变频电路和低噪声放大器等微波组件中高密度通孔薄膜电路基板的研制.     

Quaternary static latch circuit

A new voltage-mode quaternary CMOS static latch circuit is presented. Only devices available in a standard digital CMOS fabrication technology—enhancement-mode NMOS and PMOS transistors with single threshold voltage values—are used. No depletion-mode devices or special transistor threshold voltages are required. Three reference voltages and ground are used to define the logic levels. The operation of the quaternary latch is experimentally verified. Using data for a standard 2-micron digital CMOS fabrication technology, best- and worst-case on-chip setup and hold times are estimated, using simulation, to be approximately 2.8 ns and 6.8 ns, respectively.     

混合集成电路用无寄生参数载体

本文简介两种混合集成电路用无寄生参数载体的设计、制作和实验结果.无电容载体的电容量为0.0007pF,无电感载体的电感量可根据需要控制.与石英载体,梁式引线载体以及玻璃钝化载体相比,不论在性能上或者强度上都具有明显的优点.应用上述载体,可使电路易于匹配,降低功耗,提高传输效率和频率稳定度,尤其适用于高频段宽带电路.     

OLED有源驱动TFT阵列的一种测试方法

提出了一种检测有源驱动OLED TFT阵列的方法,这种电流检测方法是结合TFT的制作工艺进行的. 在只增加一块光刻版的情况下,有效地解决了在含有2个TFT的单元像素电路中,检测驱动管困难的难题. 这种检测方法能够进行快速的全屏检测,具有精度高,对TFT阵列无损伤的特点.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

High performance MOS integrated circuit using the ion implantation technique

Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 /spl Omega//spl times/cm substrate material and having 1-/spl mu/m channel length. Essential fabrication details and circuit behaviors are described.     

Statistical Simulation for Process Design and Optimization in IC Manufacture

An approach to multidimensional statistical simulation for process design and optimization in IC manufacture is proposed. It essentially takes account of the sensitivity of circuit parameters to the random variability of process parameters. The approach is implemented in an algorithm and software for process statistical analysis and optimization. The response-surface methodology and pattern-recognition techniques are used for the approximation of relations between process and circuit parameters. The capabilities of the approach are evaluated from simulated and measured data on the fabrication of transistors by routine bipolar and CMOS technologies.