Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

Simulating and modeling the breakdown voltage in a semi-insulating GaAs P+N junction diode

This work aims to determine the characteristic PN junction diode, subject to a reverse polarization, while I （breakdown voltage） of the inverse current in a GaAs specifying the parameters that influence the breakdown voltage of the diode. In this work, we simulated the behavior of the ionization phenomenon by impact breakdown by avalanche of the PN junctions, subject to an inverse polarization. We will take into account both the trapping model in a stationary regime in the P＋N structure using like material of basis the Ⅲ-Ⅴ compounds and mainly the GaAs semi-insulating in which the deep centers have in important densities. We are talking about the model of trapping in the space charge region （SCR） and that is the trap density donor and acceptor states. The carrier crossing the space charge region （SCR） of W thickness creates N electron-hole pairs： for every created pair, the electron and the hole are swept quickly by the electric field, each in an opposite direction, which comes back, according to an already accepted reasoning, to the crossing of the space charge region （SCR） by an electron or a hole. So the even N pair created by the initial particle provoke N2 ionizations and so forth. The study of the physical and electrical behaviour of semiconductors is based on the influence of the presence of deep centers on the characteristic I（V） current-tension, which requires the calculation of the electrostatic potential, the electric field, the integral of ionization, the density of the states traps, the diffusion current of minority in the regions （1） and （3）, the current thermal generation in the region （2）, the leakage current in the surface, and the breakdown voltage.     

p^＋—n^——n结的势垒分布

GaP:N绿色LED发光效率的提高有赖于对其结构参数的优化。根据载流子分布的连续性,由泊松方程自治求解,得出了半导体n^--n结势垒分布的计算方法。在此基础上,计入n^-区内的电位降,计算了商用光二极管p^ -n^--n结构的势垒分布,为整体结构的参数优化准备了必要的条件。     

Evidence of hole direct tunneling through ultrathin gate oxideusing P+ poly-SiGe gate

P⁺ poly-Si and poly-Si_0.75Ge_0.25-gated PMOS transistors with ultrathin gate oxides of 25 and 29 Å were used for this study. The difference in the gate work function was used to determine the mechanisms of gate tunneling current in such thin gate oxides, Under negative gate bias (inversion bias), it was found that the source/drain terminal serves as a source of holes for small V_g value, and as gate bias increases (more negative), it becomes a hole sink. These observations can be interpreted in terms of two competing mechanisms. For the first time, hole direct tunneling is reported, Hole direct tunneling is the dominant mechanism for -2 Vg<0 V. For Vg<-2 V, electron direct tunneling is dominant. Electron-hole pair generation by the tunneling electrons starts to dominate over hole direct tunneling only for V_g<-4 V     

Effect of base parameters on signal-to-noise ratio in silicon P+-N-N+ photoparametric upconverter diodes

The choice of base region parameters resulting in the maximum signal-to-noise ratio is discussed for silicon P⁺-N-N⁺ photoparametric upconverter diodes. It is shown that for the shot noise limited case, if the dark current is mostly due to thermal generation in the space charge layer, $\text{α}\text{l}{}_{\mathrm{b}}\text{= 1·256}$ results in the best SNR. For the thermal noise limited case, the optimum base parameters are found for different wavelengths of incident radiation.     

Small-signal impedance of gold-doped P+-N-N+silicon diodes

Experimental results of impedance measurements on a long-base, gold-doped silicon diode show a substantial inductive effect. Various terminal characteristics are given and discussed with respect to possible contributing mechanisms.     

A comparison between N+-P-P+and P+-N-N+silicon IMPATT diodes

A one-dimensional large-signal computer program that incorporates the material parameters of Si in an exact manner has been employed to compare the efficiency, power output, and other important operating characteristics of both complementary structures of Si IMPATT diodes. The results presented here differ greatly from those already reported by other authors.     

Back-gate bias enhanced band-to-band tunneling leakage in scaledMOSFET's

The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT. Each of the three shows different dependencies on back-gate bias. As a result, the bulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage. Additional experiment highlights the effect of the increased bulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT. This sets the bulk BTBT a significant constraint to the low-voltage, low-power, high-density CMOS integrated circuits employing the back-gate reverse bias. In this work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

6H-SiC p+-n junctions fabricated by berylliumimplantation

The use of beryllium (Be) as an alternate p-type dopant for implanted silicon carbide (SiC) p⁺-n junctions is experimentally demonstrated. The implanted layers have been characterized with photoluminescence (PL) as well as secondary ion mass spectrometry (SIMS) measurements. In comparison with boron implanted p ⁺-n junctions, Be-implanted junctions show improvement in the forward characteristics while exhibiting slightly higher reverse leakages. The activation energies extracted from the forward conduction and reverse leakage characteristics of the Be-diodes are 1.5 eV, and 0.13 eV, respectively. Moreover, activation energy extraction in the forward ohmic region reveals the Be impurity level at 0.38±0.04 eV. The minority carrier lifetime extracted from reverse recovery measurements is as high as 160 ns for the Be-diodes compared to 82 ns obtained for the B-diodes     

Specific contact resistivity of TiSi2to P+and n+junctions

Specific contact resistivities of the Al/TiW/TiSi2/Si system are characterized. It is found that without a TiW barrier layer, Al can penetrate through the TiSi2layer and significantly affect the TiSi2/Si interfacial contact resistance. Intrinsic TiSi2contact resistivities to n⁺and p⁺silicon are characterized with a TiW barrier between the silicide and the aluminum. TiSi2contact resistivity to n⁺silicon is found to be about one order of magnitude lower than that of Al to n⁺silicon. However, TiSi2to p⁺silicon contact resistivity is higher than that of Al to p⁺silicon and is very sensitive to the boron implant dose.     

Damage removal/dopant diffusion tradeoffs in ultra-shallowimplanted p+-n junctions

The tradeoffs between implant damage annealing and shallow junction formation are investigated. For very-low-energy amorphizing implants the time for damage anneal has a fourth-power dependence on depth below the Si surface. The depth effect depends on the type of amorphizing ion. It is shown that as a result, implanted B in Ge-preamorphized Si diffuses with no detectable self-interstitial supersaturation if the damage is <600 Å deep. Conditions for forming defect-free, shallow p⁺-n junctions are described in design curves and comparisons are made between several junction-formation approaches. Implantation of B at energies below 2 keV offers an attractive way of achieving 500-Å junctions     

4H-SiC trench MOSFET with an integrated Schottky barrier diode and L-shaped P+ shielding region

A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper. The device features an integrated Schottky barrier diode and an L-shaped P⁺ shielding region beneath the gate trench and aside one wall of the gate trench (S-TMOS). The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction, which significantly reduces reverse recovery charge (Q_rr) and reverse turn-on voltage (V_F). The L-shaped P⁺ region effectively shields the coupling of gate and drain, resulting in a lower gate–drain capacitance (C_gd) and date–drain charge (Q_gd). Compared with that of conventional SiC trench MOSFET (C-TMOS), the V_F and Q_rr of S-TMOS has reduced by 44% and 75%, respectively, with almost the same forward output current and reverse breakdown voltage. Moreover, the S-TMOS reduces Q_gd and C_gd by 32% and 22%, respectively, in comparison with C-TMOS.     

Ti-TiO2 gated MOS diode light sensor

This paper explores the possibility of improving the performance of a resistive TiO₂-Ti gated MOS diode as a light sensor. The original device proposed by Whelan has a limitation on the maximum useful scan frequency to several hundreds of Hz. In this paper, a new construction was proposed to improve the maximum scan frequency and extend this limitation to about 10 KHz. It is also shown that the frequency can be further improved to about 1 MHz by reducing the gate resistance and capacitance. The limitation in the growth cycle is mainly due to charging of the gate electrode and output resistance. No attempt has been made for the optimization of the device design. The resolving power was also been considered.     

Hole and electron currents in diffused P+-N-N+diodes and IIL structures

The hole current due to recombination in the N epitaxial layer is calculated and compared to the electron current injected into the diffused P region. A formula is given and results are compared with computed currents for both wide and narrow (e.g., IIL) structures, including heavy doping effects.     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Near state-of-the-art power in p+-n-n+D-band IMPATT diode on a wafer with ramped n-n+interface

Fabrication of near state-of-the-art (P0= 110 mW, η = 4.85 percent p⁺-n-n⁺D band (f = 124 GHz) Si IMPATT diode on a wafer with ramped n-n⁺interface is described. Introduction of a critical annealing step, prior to p⁺diffusion, in the fabrication sequence of the diode has been found to yield the above results. Possible reasons for power and efficiency enhancement has been discussed.     

Admittance of a forward-biased P-N+junction diode

Numerical solutions of the basic semiconductor transport equations are used to analyze the ac behavior of a forward-biased diode.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.