Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

A new technique of erasing nonvolatile memory (NVM) devices based on nitride storage (SONOS) with bottom oxide thickness in the range of 30 /spl Aring/ has been developed. Oxide thickness in this range is necessary to minimize the undesirable effects of gate disturb while still enabling a low-voltage operation to maximize the cost benefit of SONOS memories. To erase such bitcells, Fowler-Nordheim tunneling (FNT) is preferred over hot-hole injection (HHI) due to the less damaging nature of FNT. However, FNT alone cannot be used to erase the device completely due to erase saturation limitations. Hence, the new "combination-erase" technique combines both FNT and HHI erase to achieve a fast and controlled erase. Furthermore, by using FNT erase at higher field conditions, and HHI erase at lower field conditions, the reliability of the bitcell is also improved.     

Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS)

The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered silicon-oxide-nitride-oxide-semiconductor (SONOS) (H. T. Lue, et al., in IEDM Tech. Diag., p. 331) device are extensively studied. The lateral BBHE profile is extracted by fitting the experimental current-voltage (I-V) characteristics with 2-D simulation. The results suggest that, after BBHE injection, the local channel potential barrier is reduced, which, in turn, raises the Vt of the p-channel device. The 2 bit/cell operation methods and second-bit effect (2 bit interaction) are examined. The effects of channel-length scaling, junction profile, and effective oxide thickness of the gate stack are also addressed     

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.     

FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part I: Experimental

A new structure for an n-channel Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) and its novel write-erase characteristics are described. The new structure is a modification of the previously reported FCAT (FCAT-I) memory device. The key improvement is better coupling between the floating gate and the control gate. This makes Fowler-Nordheim tunneling the major electron injection mechanism in the floating gate. The p⁺-p junctions placed outside the channel area are self-aligned with the floating gate and have an important role in crowding and raising the electron injection field. The device can operate in both write and erase modes at high-speed (≥ 50 ns) and low-voltage (≤15 V) conditions using only positive pulses. Another useful feature is the saturation of the high level threshold voltage independent of write pulse width greater than 50 ns. Reliability of this device is as good as that of FCAT-I.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Investigation of Drain Disturb in SONOS Flash EEPROMs

The mechanism of drain disturb is studied in silicon-oxide-nitride-oxide-silicon Flash electrically erasable programmable read-only memory cells. It is shown that disturb is a serious problem in programmed cells and is caused by injection of hot holes from substrate into the oxide/nitride/oxide stack. The origin of these holes is identified by analyzing the influence of halo doping, channel doping, and channel length scaling on drain disturb. Band-to-band tunneling at the drain junction is normally the dominant source of these holes. It is also shown that holes generated out of impact ionization of channel electrons become dominant in cells with high channel leakage (especially at lower channel lengths). Finally, the effect of repeated program/erase cycling on drain disturb is studied. Drain disturb becomes less severe with cycling, the reasons for which are determined using gate-induced drain leakage measurements and device simulations     

Performance Evaluation of Field-Enhanced P-Channel Split-Gate Flash Memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler–Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of$sim$2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.     

Simulation of Schottky barrier MOSFETs with a coupled quantuminjection/Monte Carlo technique

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 μm Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 Å gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage     

New programming and erasing schemes for p-channel flash memory

In this work, a new programming scheme using a forward substrate bias during BBHE injection and a two-step erasing scheme has been suggested to improve the performances of p-channel flash memory. It has been found that applying a forward substrate bias increases the electron injection efficiency and improves the cell's endurance characteristics. The two-step erasing scheme, where a channel erase cycle is added after the source erase operation, is found to reduce the gate current degradation and also to improve the cell's endurance characteristics     

Characteristics of interface-doped MNOS memory devices

The results of an investigation of the characteristics of MNOS memory devices are given in which the interface between the oxide and nitride was doped with a few monolayers of various refractory metals. In particular, write speeds of the order of microseconds could be obtained along with retention times which could be extrapolated to many decades. No temperature dependence could be found for the decay of stored charge between 77 K and 300°C, indicating that retention is normally dominated by Fowler-Nordheim back tunneling from the interface. Long time exposure to high gate voltages and write/erase cycling in excess of 1000 cycles sharply reduces the achievable memory window, and is accompanied by the copious generation of fast surface states, at least in p-channel devices.     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

An enhanced erase mechanism during channel Fowler-Nordheimtunneling in flash EPROM memory devices

An enhanced erase behaviour observed during the channel Fowler-Nordheim (FN) tunneling erase operation was examined in details. This enhanced erase occurs when a high p-well voltage is used, with the source and drain junctions of the cell left floating, during the erase operation. Our investigation indicates that the floating source and drain take on a high junction voltage during the p-well voltage transient. This causes transient band-to-band tunneling, and in some cases, junction avalanche breakdown, to occur in the source and drain junctions. As a result, hot-hole injection into the floating gate takes place to create this enhanced erase phenomenon     

A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application

A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated.     

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A novel 2-bit/cell nonvolatile memory (NVM) with metal-oxide-nitride-oxide-semiconductor (MONOS) asymmetric double gate (ADG) MOSFET structure is proposed. With the double gate structure, the two conducting channels provide the ability to store 2 bits in a cell. Program and erase can be performed by channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling respectively. The read operation and the array structure of the proposed novel NVM are also studied and described in this paper.     

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

An erase model in double poly-Si gate n-channel FAMOS devices

The existence of a poly-Si control gate in an n-channel FAMOS makes the erase characteristics due to ultraviolet light (UVL) illumination different from those of conventional p-channel FAMOS's without control gates. The difference in erasing times between these two types of FAMOS has been explained by the attenuation of UVL in the control gate. However, it was clarified experimentally and analytically in n-channel FAMOS that UVL is propagated horizontally in an optical guide formed between the control gate and substrate and is then absorbed by the floating poly-Si gate. The absorbed UVL intensity in the floating gate through the proposed optical guide is calculated to be 10⁹times stronger than that transmitted directly through the control gate whose thickness and absorption coefficient are assumed to be 3500 Å and 10⁶cm^-1, respectively. The proposed optical guide model is supported in experiments that erase time does not depend on the thickness of the control gate (2400- and 3600-Å devices are compared) and erase time in a device whose optical guides are open only on one side and the other side is covered by the control gate is about 2 times longer than that in a device which has two optical guides open on both sides.     

A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase

In this work, we describe a novel SONOS device suitable for future nonvolatile flash memories. Substrate hot-hole injection (HHI) through a bottom oxide is used for write and gate tunneling through a thin top oxide is employed for erase. We present device DC and dynamic characteristics at low voltages (<10 V) for SONOS devices with a gate dielectric stack consisting of a 3.8 nm bottom oxide, 1.5 nm nitride and 3.0 nm top oxide. We obtain a reduction in power consumption by 4 orders of magnitude, an improvement in retention by 90%, and an improvement in subthreshold swing by 40% with a novel write/erase technique compared with Substrate HHI for erase and channel hot electron (CHE) injection for write.