Elimination of truncation and round off error and enhancement of stability using a new split loop DPLL

In contrast with the conventional split loop digital phase lock loop, a new loop is presented in this paper that differs from the earlier version principally by design aspects. It incorporates an additional phase modulation input along with its frequency modulation input in the digital controlled oscillator. It is capable of eliminating the deleterious effects of rounding and truncation error with faster signal accusation. Higher loop stability is also achievable using the new split loop digital phase lock loop. Furthermore, radio frequency filtering is done using an In phase and Quadrature phase (IQ) voltage controlled oscillator to avoid interaction between the loop filter and the radio frequency filter. Copyright © 2011 John Wiley & Sons, Ltd.     

Optical Phase Locking by Local Oscillator Phase Dithering

A new type of optical phase-locked loop (OPLL), called the dither loop, is mathematically analyzed. The dither loop extracts a phase-error signal by applying a small phase disturbance to the local oscillator laser, and synchronously demodulating the resulting power fluctuation in the output signal of the receiver. The dither loop is superior to other OPLL designs, because it does not need the transmission of a residual carrier, it employs a 180deg/3-dB hybrid, an ac-coupled front end, and it accepts a large variety of input signals. Furthermore, in a dither loop, the amount of power which is fed to the phase-locking branch can be adaptively controlled within the receiver. The analysis first focuses on an expression for the phase detector gain in a dither loop. Using a linearized model, the phase-error variance due to phase dithering, white frequency noise induced phase noise and shot noise is evaluated. A simplified expression for the power penalty generated by the phase dither signal is presented. In a more complex calculation, the overall power penalty due to phase dithering and the residual phase error is found. This allows us to synthesize a design rule for dither loops with optimum performance measures. The design rule determines all relevant system parameters, based on specified values of the system bit rate, the laser linewidth, the photodiode responsivity and the required bit-error rate     

适用于超宽带系统的低功耗CMOS频率合成器研究

针对脉冲无线电超宽频(IR-UWB)接收系统,提出了一种低功耗频率合成器设计。合成器的设计以一个整数N分频II型四阶锁相环结构为基础,包括一个调谐范围为31%的7位压控振荡器,一组基于单相时钟逻辑的高速分频器。分频器能够合成八个由IEEE标准802.15.4a定义的频率。该集成频率合成器运用65 nm CMOS技术制造而成,面积为0.33 mm2,工作频率范围为7.5–10.6 GHz。测试结果显示,在1.2 V供电下,该合成器的3-dB闭环带宽为100 kHz,稳定时间为15 。测量相位噪声低于-103 dBc/Hz@1MHz,抵消频率为1 MHz。杂散信号功率低于低于-58 dBc。相比其他先进的合成器,提出合成器的工作电流为5.13 mA,功耗仅为6.23mW。     

A novel DSP‐based PFC‐DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity

This paper proposes a new digital signal processing (DSP)‐based phase frequency controlled digital phase locked loop. Here, a very simplistic form of fuzzy logic controller with the help of carrier phase and frequency error as input data is used to provide an acquisition aid. A frequency discriminator is employed to generate frequency error, and phase detector output is taken for phase error. This addition of an acquisition aid helps the loop to achieve the minimum acquisition time and maximum noise rejection simultaneously. An additional phase control in the digitally controlled oscillator makes the loop perform even better towards this goal. The implementation of the proposed loop is carried out on a reconfigurable logic platform using System Generator^®;, a tool from Xilinx^®; used to design real‐time DSP application. A significant improvement of time domain characteristics are observed as well as the performance in presence of additive white Gaussian noise is demonstrated in terms of the reduction in steady‐state phase jitter and enhancement in output signal to noise ratio in the proposed loop. Copyright © 2014 John Wiley & Sons, Ltd.     

Low phase-noise microwave oscillators with interferometric signal processing

Phase-noise spectral density of a 9-GHz oscillator has been reduced to -160 dBc/Hz at 1-kHz offset frequency, which is the lowest phase noise ever measured at microwave frequencies. This performance was achieved by frequency locking a conventional loop oscillator to a high-Q sapphire dielectric resonator operating at the elevated level of dissipated power (/spl sim/0.4 W). Principles of interferometric microwave signal processing were applied to generate the error signal for the frequency control loop. No cryogenics were used. Two almost identical oscillators were constructed to perform classical two-oscillator phase-noise measurements where one oscillator was phase locked to another. The phase locking was implemented by electronically controlling the level of microwave power dissipated in the sapphire dielectric resonator.     

基于光纤环选频特性的双环结构光电振荡器

提出并验证了一种借助于光纤环的选频特性实现辅助滤波的光电振荡器,利用偏振分束器(PBS)和偏振合束器(PBC)构成的双环路结构抑制掉部分光电振荡器的边模,同时借助于光纤环的光学梳状频率特性,对振荡器环路中的光信号模式再次进行选择,既起到边模抑制的作用,又提高了光电振荡器谐振腔的Q值.仿真结果表明:采用光纤环辅助滤波有利于光电振荡器的边摸抑制和单模输出,在保证光电振荡器输出低相位噪声和高频谱纯度微波信号的情况下,边模抑制比超过160 dB,模式间隔达到370 MHz,降低了对电域带通滤波器的性能要求,是一种新的光电振荡器设计方案.     

一种快捕获宽调节范围的锁相环

提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获时间为150ns;输出频率为640MHz时,均方根抖动为39ps.     

一种伪差分两级环形振荡器的设计

设计了一种伪差分两级环形振荡器,可为锁相环提供8 GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65 nm CMOS工艺进行设计与仿真。结果表明,在1.2 V电压下,振荡器的功耗为6.9 mW,1 MHz频率处的相位噪声为－82.104 5 dB,满足高速SerDes接口的设计要求。     

短波段频率合成器的设计与调试

设计了基于锁相环的短波段正弦信号合成器,其工作原理为原始的正弦波输出信号由压控振荡器产生,经芯片分频输出一个低频方波信号,参考信号采用Q值较高的晶体产生,然后输出到芯片的分频,在芯片内部输出一个低频方波信号,两路低频方波信号同时由芯片内部的数字鉴相器进行比相,输出一个反映相位误差值的双路差分电压信号到有源环路低通滤波器,经它滤波形成近似直流的信号,控制压控振荡器的变容管反相偏置电压来调整振荡频率。仿真结果达到预期要求。     

用于卫星电视调谐器的整数频率综合器设计

设计了一个用于模拟卫星电视调谐器的整数频率综合器.锁相环本振输出频率范围覆盖1.25GHz到2.8GHz,参考频率可配置为62.5kHz或31.25kHz.环路滤波器采用三阶有源滤波器,环路带宽为1kHz.电荷泵输出电流可配置为50μA或250μA.压控振荡器(VCO)采用差分反馈型结构,在偏离中心频率10kHz处的相位噪声小于-76dBc/Hz.分频器采用脉冲吞咽型结构,有15位控制位.P计数器从输入到输出只经过两个触发器和一个逻辑门,能有效减少由多级异步分频器产生的相位噪声.电荷泵充放电电流的不匹配会恶化参考杂散,这里引入了对电流过冲不匹配的考虑,在鉴频鉴相器(PFD)和电荷泵中加入了减少充放电电流过冲的措施.电路采用0.18μm RFCMOS工艺实现,面积1.3mm*1.5mm.     

一种小体积X波段频率合成器设计

介绍了一种小体积频率合成器的设计，该频率合成器通过直接数字频率合成器（DDS）产生线性调频信号，通过锁相环产生固定二本振信号，通过锁相环（PLL）与2 倍频器产生一本振信号，通过变频部分完成二次混频产生射频激励信号。同时采用现场可编程门阵列（FPGA）完成DDS 控制以及与系统通讯，电源控制部分产生各种电源。     

一种具有相位噪声跟踪补偿的全数字锁相环频率合成器

为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。     

A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset     

A precise 90/spl deg/ quadrature OTA-C oscillator tunable in the 50-130-MHz range

We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-/spl mu/m CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.     

用于锁相环快速锁定的鉴频鉴相器设计

针对鉴频鉴相器(PFD)的盲区现象对锁相环路的锁定速度的影响,设计了一种PFD结构,可以实现锁相环路的快速锁定。该结构在传统PFD的基础上,利用内部信号的逻辑关系进行逻辑控制,其输出特性呈现非线性;在输入相位差大于π时,抑制了复位脉冲的产生,避免了输入时钟边沿的丢失,有效消除了盲区,加快了锁相环的锁定速度。设计采用SMIC 0.18μm标准CMOS工艺,采用全定制设计方法对该PFD结构进行了设计、仿真分析和验证。结果表明,采用该PFD结构的锁相环,在400 MHz工作频率下锁定时间为2.95μs,锁定速度提高了34.27%。     

X 波段快速跳频频率综合器的设计与实现

本文主要以频率合成器在毫米波探测器中的应用为背景,对快速、高稳定、低相噪、小体积频率源进行研究。 首先,本文介绍了设计方案及其优点,并且着重分析了环路带宽的选择对频率源建立时间和相位噪声对系统的影响, 设计实现了一套模块化的适用于毫米波探测器中的频率源系统,本文使用了乒乓式的锁相环保证了快速的跳频时间和 低相位噪声,使用了matlab 分析跳频本振的跳频时序,并且分析振动实验的结果。     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

锁相环路的特性及其应用

锁相环路是一种以消除频率误差为任务的自动控制电路,由鉴相器、环路滤波器和压控振荡器组成,具有自动跟踪、锁定后没有频差、良好的窄带特性和易于集成的特点,广泛应用于倍频、分频和混频以及滤波、模拟数字信号的调制和解调、信号检测和接收、频率合成等许多技术领域,是现代电子产品中非常重要的部件。对环路结构和特性进行分析及锁相环路在不同领域的应用进行介绍,通过框图进一步阐述相应内容,使广大读者进一步认识锁相环路及其相应的产品。     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

DDS+PLL宽带频率合成器的设计与实现

采用DDS PLL技术实现频率合成器,其特点是宽频带(3～6 CHz)、小步进(1 kHz)、低相位噪声,频率捷变.对其进行了理论分析,描述了宽频带和小步进的实现方式,相位噪声以及频率捷变的确定问题.频率合成器由DDS、锁相环路、压控振荡器、放大电路、参考信号和数据处理等电路组成.压控振荡器的信号经过功分、分频、下混频,滤波后和晶振信号在锁相环路进行鉴相,生成误差电压来控制VCO的频率,同时通过改变DDS的频率得到小步进、低相位噪声的输出信号.