一种专用MCU芯片可测性设计的实现

由于ＭＣＵ芯片的结构非常复杂,设计时采用一般的从结构出发的可测性设计技术（包括ＤＦＴ和ＢＩＳＴ）将使电路的规模大大增加。根据ＭＣＵ具有指令系统的特点,从功能测试的角度出发,提出了一种在ＭＣＵ设计中加入规模很小的模式选择电路,对部分电路作较小改动就使芯片内的各块电路都可被测试的方法。在完成了可测性设计后进行了仿真。     

基于嵌入式内核SOC IDDQ可测试设计方法

由于电路门数增大和晶体管亚阈值电流升高，导致电路的静态漏电流不断升高，深亚微米工艺SOC(系统芯片)IC在IDDQ测试的实现方面存在巨大挑战．虽然减小深亚微米工艺亚阈值漏电开发了许多方法，如衬底偏置和低温测试，但是没有解决因为SOC设计的规模增大引起漏电升高的问题．首先提出了SOC设计规模增大引起高漏电流的可测试性设计概念．然后制定了一系列适合于SOC的IDDQ可测试设计规则．最后提出了一种通过JTAG指令寄存器控制各个内核电源的SOC IDDQ可测试设计方法．     

多电压SoC引线压焊供电引脚分配及电源网络拓扑优化

针对较大电压降易导致电压岛内电路宏模块供电不足,引起电路失效的问题,基于引线压焊技术封装芯片,提出一种面向多电压技术的电压岛供电引脚分配及电源网络拓扑优化方法.首先根据电压岛的物理布图信息,采用弹簧模型确定电压岛供电引脚位置实现电压降优化;然后通过建立稠密的虚拟电源网络,利用增量式方法完成电源网络的拓扑优化.通过对GSRC标准电路测试的实验结果表明,与固定供电引脚方法相比,文中提出的供电引脚分配方法平均降低电压降26.1%;而电源网络拓扑优化方法产生的非规则网络,使得电源网络布线面积较规则电源网络的布线面积平均降低84.5%.     

中国芯C*Core设计及应用

随着集成度的提高,在嵌入式应用中,人们倾向于把CPU、存储器和一些外围电路集成到一个芯片上．构成所谓的系统芯片（简称为SOC）,而把SOC上的那个CPU成为CPU芯核。大部分嵌入式CPU都是针对某个应用。文中介绍了苏州国芯设计的C＊Core及其SOC设计平台,进一步了解由我国国内自行设计的CPU的特点及开发前景。     

MCU可测性设计的实现

由于 MCU(Micro-Controller Unit)的结构非常复杂 ,因此若在设计时采用一般数字电路设计的从结构出发的 DFT(Design For Testability)技术 (包括扫描设计和 BIST—— Built-In Self-Test)将使电路的规模急剧增大。本文从功能测试的角度出发 ,提出了一种在 MCU中加入规模很小的模式选择电路 ,对部分电路作较小改动 ,就使芯片内的各块电路都可被测试的方法。在完成了 MCU 的可测性设计(Testable Design)后进行了仿真     

时钟芯片的低功耗设计

在时钟芯片设计的各个层次上深入探讨了影响时钟芯片功耗的主要因素,确定了电路功耗主要来源与振荡电路和分频电路。在电路实现过程中,通过采用不同工作电压和对主要功耗电路的结构和参数进行优化设计等多种手段来控制功耗。通过1.2滋m工艺流片验证,在工作电压为5V时,芯片工作电流为0.17mA,实现了低功耗时钟芯片的设计。     

ASIC集成电路的可测性设计与技术实现

ASIC集成电路设计开发中的隐含逻辑瑕疵与电路故障是芯片实现的最大困境,针对不同特性的电路提出了内部逻辑扫描、存储器内建自测试、边界扫描链插入以及ATPG自动测试向量生成的解决方案与技术方法,实现了SOC设计开发中逻辑与成片电路的主动侦测与跟踪寻径,经实践证明这些方法大大提高了复杂SOC研制的成功率.     

航空电源电池管理系统BMS设计

针对航空电源电池管理系统可靠性的需要,研究了现有的电池管理系统的特点,设计了一种基于飞思卡尔MC9S12XET256和Linear 6804-2的电池管理系统。该系统硬件包括电池组电池电压测量电路、温度测量电路、电池充放电电压电流测量电路以及基于Linear 6820的iso SPI和SPI转换电路;软件设计包括电池电量数据读取、温度数据读取、充放电电流计算、均衡控制、电池荷电状态(SOC)与健康状况(SOH)的计算以及主控芯片的任务管理与通信。试验测试表明,该系统运行稳定,测试精度高,可在电池管理实际工程中使用。     

一种低压曲率校正带隙基准电压源

基于标准0.6umCMOS工艺,设计依据在亚阈值区工作的一阶温度补偿电路,采用VPTAT电压驱动曲率校正电路,对一阶温度补偿电路进行高阶温度补偿,获得了一种电路结构简单,性能较好的带隙基准源。经过Hspice仿真,仿真结果表明电路可以在-10-150范围内,平均温度系数约9.9ppm/oC;工作电压为1.4V。该带隙基准源可应用于高精度模数转换器(ADC)、数模转换器(DAC)和系统集成芯片(SOC)中。     

SOC可测试性设计与测试技术

超深亚微米工艺和基于芯核的设计给芯片系统(system-on-a-chip,SOC)测试带来了新的问题．对SOC可测试性设计与测试技术的国际研究现状及进展进行了广泛而深入的综述．从芯核级综述了数字逻辑、模拟电路、存储器、处理器4类芯核的可测试性设计与测试技术,从系统级综述了测试激励、测试响应和测试访问机制等SOC测试资源的设计以及压缩／解压缩与测试调度等测试资源划分、优化技术,并介绍了2个标准化组织开展的SOC测试标准工作．最后,展望了SOC测试未来的发展方向．     

一种新型矿用本安电源保护电路的设计

在分析传统矿用本安电源保护电路优缺点的基础上,提出了一种采用LM339比较器和MAX4080SASA电流检测芯片的新型矿用本安电源保护电路设计方案,并详细分析了该设计方案的原理和特点,为矿用本安电源的设计提供了一种高质量的解决方案。     

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.     

基于单片机的双电源切换装置的设计与实现

针对不间断供电的广泛需求，基于对电压采样、检测和比较的工作原理，利用单片机对电源状况进行检测和判断并进行相应的控制，实现了双电源供电的自动切换，从硬件结构、软件煽制和抗干扰措施三方面进行了较详细的讨论。     

Loss-aware routing algorithm for photonic networks on chip

Photonic network on chip was introduced as an efficient communication platform to overcome the existing challenges in traditional networks on chip. Optical networks provide high bandwidth and low power dissipation infrastructure. Insertion loss is one of the important parameters in photonic networks on chip. In this study, we propose a solution in routing algorithm level in order to reduce insertion loss in photonic network on chip, by passing packets through paths with lower number of optical elements. Simulation results reveal that a novel approach in the routing level decreases insertion loss as much as possible, energy consumption and optical power budget. Our proposed routing has 29.05% less insertion loss under all2all traffic pattern for blocking torus topology, and it has about 12.37% less insertion loss for TorusNX topology in comparison with primary dimension-ordered routing. Proposed routing algorithm increases both the network bandwidth and scalability.     

基于单片机的车载电源控制系统设计

为了实现车载电源可靠工作,设计了一种基于单片机的电源控制系统,该系统使用单片机芯片C8051F020为主控芯片,对各电源单元上报的数据进行分析判断,通过外接彩色液晶显示屏和语音报警芯片ISDl420分别实现电源的状态显示和故障语音报警,从而实现了对车载电源的状态监控及管理,使电源更加安全地工作;通过该系统在车载电源系统产品中的实际应用,证明了该系统能有效和迅速地自动控制电源电压,在电源保护或故障时及时给出显示和语音报警提示,使用户能及时了解故障问题并作相应处理。     

基于单片机控制的程控开关电源研究

提出了基于单片机控制的程控开关电源解决方案,给出的主电路采用典型单端反激电路模式,控制电路采用51单片机为核心芯片,结合AD采样解决了控制功率开关管导通与关断信号PWM的控制问题.实现了开关电源输出电压为0.1 V/级的程控调节,其调节范围最大可达额定输出的76%.这种工作方式的建立使开关电源在设计上具有使用器件少、实...     

A novel mapping algorithm for three-dimensional network on chip based on quantum-behaved particle swarm optimization

Mapping of three-dimensional network on chip is a key problem in the research of three-dimensional network on chip. The quality of the mapping algorithm used directly affects the communication efficiency between IP cores and plays an important role in the optimization of power consumption and throughput of the whole chip. In this paper, basic concepts and related work of three-dimensional network on chip are introduced. Quantum-behaved particle swarm optimization algorithm is applied to the mapping problem of three-dimensional network on chip for the first time. Simulation results show that the mapping algorithm based on quantum-behaved particle swarm algorithm has faster convergence speed with much better optimization performance compared with the mapping algorithm based on particle swarm algorithm. It also can effectively reduce the power consumption of mapping of three-dimensional network on chip.     

基于TOP245Y芯片的高可靠性电源设计

介绍了一种采用TOP245Y智能控制集成芯片设计的开关电源的方法，给出了基于TOP245Y的单端反激式开关电源的设计电路。和对外围电路的设计进行了分析说明。此电源具有低成本，高效率，小尺寸，全密封式的特点。     

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

To reduce the interconnect delay and improve the chip performance, three-dimensional (3D) chip emerged with the rapid increasing of chip integration and chip power density. Therefore, thermal issue is one of the critical challenges in 3D IC design due to the high power density. Multiple Supply Voltages (MSV) technique provides an effcient way to optimize power consumption which in turn may alleviate the hotspots. But the voltage assignment is limited not only by the performance constraints of the design, but also by the physical layout of circuit modules since the modules with the same voltage should be gathered to reduce the power-network routing resource. Especially in 3D designs, the optimization using MSV technique becomes even more complicated since the high temperature also inffuences the power consumption and delay on paths. In this paper, we address the voltage-island generation problem for MSV designs in 3D ICs based on a mixed integer linear programming (MILP) model. First, we propose a general MILP formulation for voltage-island generation to optimize thermal distribution as well as power-network routing resources while maintaining the whole chip performance. With the thermal-power interdependency, an iterative optimization approach is proposed to obtain the convergence. Experimental results show that our thermal-aware voltage-island generation approach can reduce the maximal on-chip temperature by 23.64% with a reasonable runtime and save the power-network routing resources by 16.71%.     

基于部分随机行走的电源线/地线(P/G)网络快速求解方法

介绍一种基于随机行走方法与松弛迭代(SOR)算法相结合的快速电源网络求解方法，它先将P／G网分为若干块，然后用简化的随机行走方法求取电路块边界结点的电压，最后采用松弛迭代算法求出电路块内部结点的电压．同时还给出了一种电路块从对角顶点向中央求解的策略，并将此方法推广到采用RLC瞬态网络的求解．大量的实验数据表明，受限于P／G网供电PAD的数目较少这一现实，随机行走方法的效率比较低，在此情形下，该方法比随机行走方法快20倍．