共查询到20条相似文献,搜索用时 15 毫秒
1.
《Solid-State Circuits, IEEE Journal of》2006,41(10):2224-2232
This paper describes a fully differential 1-tap decision feedback equalizer in 0.18-$muhbox m$ SiGe BiCMOS technology. The circuit is capable of equalizing NRZ data up to 40 Gb/s. A look-ahead architecture is employed with modifications to reduce complexity in the high-speed clock distribution. An analog differential voltage controls the tap weights. The design is fabricated in 0.18-$muhbox m$ SiGe BiCMOS technology with a 160-GHz$f_T$ . It occupies an area of 1.5 mm$,times ,$ 1 mm and operates from a 3.3-V supply with 230-mA current. It is the first feedback equalizer at 40 Gb/s. 相似文献
2.
《Solid-State Circuits, IEEE Journal of》2006,41(8):1764-1771
This paper addresses the problem of 5–6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-$muhbox m$ CMOS technology, comprises a single-ended voltage–voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a$-$ 6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF),$-$ 3.5-dBm minimum IIP3 and$+$ 34.5-dBm minimum in-band IIP2 and$+$ 21-dBm out-of-band IIP2. 相似文献
3.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2058-2066
An adaptive equalizer incorporates spectrum-balancing technique to achieve high speed and low power dissipation. Obviating the need for slicers, this circuit compares the low and high frequency components of the data spectrum and adjusts the boosting accordingly. Fabricated in 0.13-$muhbox m$ CMOS technology, this circuit achieves a data rate of 20 Gb/s while consuming 60mW from a 1.5-V supply. 相似文献
4.
《Solid-State Circuits, IEEE Journal of》2006,41(4):781-792
Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-$muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions. 相似文献
5.
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-mum CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one 相似文献
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设计了一种用于SDH系统STM-64(10Gb/s)速率级光接收机中的BiCMOS放大电路,包括NMOS共栅-共源前置放大器和差分式BiCMOS主放大器;各个放大器中都引入了负反馈;并精选了元器件参数,采取了提速措施,以保证放大电路在低功耗下工作在10Gb/s或更高速率上.实验结果表明,所设计的放大电路在10Gb/s速率上,主放大器输入动态范围为42dB(3.2~500mV),50Ω负载电阻上的输出限幅约为250mV,小信号输入时的最高工作速率达到12Gb/s,放大电路可采用1.8~5.6V电源供电,平均功耗约为230mW,从而满足了光纤通信系统中的高性能要求. 相似文献
8.
A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/Pde) of 180.1 GHzOmega/mW. 相似文献
9.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2052-2057
A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-$muhbox m$ CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS$2 ^31 -1$ input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp. 相似文献
10.
采用0.25 μm SiGe双极CMOS (BiCMOS)工艺设计并实现了一种传输速率为25 Gbit/s的高速跨阻前置放大器(TIA).在寄生电容为65fF的情况下,电路分为主放大器模块、两级差分模块和输出缓冲模块.相比传统的跨阻放大器,TIA采用Dummy形式实现了一种伪差分的输入,减小了共模噪声,提高了电路的稳定性;在差分级加入了电容简并技术,有效地提高了跨阻放大器的带宽;在各级之间引入了射极跟随器,减小了前后级之间的影响,改善了电路的频域特性.电路整体采用了差分结构,抑制了电源噪声和衬底噪声.仿真结果表明跨阻放大器的增益为63.6 dBQ,带宽可达20.4 GHz,灵敏度为-18.2 dBm,最大输出电压为260 mV,功耗为82 mW. 相似文献
11.
A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology 总被引:1,自引:0,他引:1
Chu M. Jacob P. Kim J.-W. LeRoy M. R. Kraft R. P. McDonald J. F. 《Solid-State Circuits, IEEE Journal of》2010,45(2):380-390
12.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2067-2076
A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18$muhbox m$ SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel$2^7-1$ PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p. 相似文献
13.
《Solid-State Circuits, IEEE Journal of》2006,41(8):1908-1918
This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-$muhbox m$ process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095$hbox mm^2$ die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply. 相似文献
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利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm. 相似文献
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A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology. 相似文献
18.
针对短沟道晶体管数学模型高复杂度问题,文章提出了一种适用于刻画短沟道晶体管模型的gm/Id方法.该方法主要通过建立电路指标与晶体管尺寸的关系来优化电路性能.采用gm/Id方法设计了一种低功耗、低噪声和宽带宽的2.5 Gbit/s跨阻放大器,并进行了版图后仿真,仿真结果表明,当光电二极管电容为250 fF、跨阻放大器的低... 相似文献
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A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm2 相似文献