铝电解电容器容量不稳定现象分析与控制

铝电解电容器的无容量主要是因为接触电阻大、裂箔、铆接不良、铆接花瓣小、正极箔表面箔灰厚及原箔腐蚀太深而造成.容量时有时无主要是铆偏、箔片断片、抽芯、铆花毛刺、导针毛刺、铝箔边缘毛刺、露箔等原因而造成.在生产过程中加强铆接、卷绕工序的质量控制,避免出现容量不稳定的现象.     

铝电解电容器制造的关键工序—柳接

铝电解电容器的正、负极通过引出箔或引出线与正、负极箔片柳接而引出，其铆接质量与电容的可靠性密切相关。铆接的方法有刺铆、压铆、超声波焊接等，铆接接触电阻是衡量铆接质量的最重要标志。本文较详细介绍了铆接的基本质量要求与质量控制方法。     

国产化铝电解电容器生产线设备

本文对近年来国营706厂研制开发的铝电解电容器生产线设备进行了概括的介绍。重点介绍:铝箔腐蚀。铝箔赋能、铝壳制造、引线闪光对焊、引线成型、引线装盒、引线与铝箔刺铆、刺铆针刃磨、芯包卷绕、真空浸渍、电容器封口、套管打印、外套热缩、联动装配等设备。     

高频低阻抗铝电解电容器生产工艺的探讨

开关稳压电源中输出滤波器用的高频电解电容器要求高频低阻抗。探讨了高频低阻抗铝电解电容器的生产工艺。刺铆卷绕:箔片、铆接点、极间距离的考虑。浸渍工艺:浸渍时间、温度等条件的确定。老练工艺:老练温度、时间、电压的斟酌。材料:电解液、铝箔、电解液、密封橡胶塞的选择。用确定的工艺制得了合格的产品。     

铝电解电容器等效串联电阻的分析及控制

文章分析了铝电解电容器等效串联电阻对产品性能的影响,讨论了等效串联电阻的构成及其影响因素,阐述了铝电解电容器生产中控制等效串联电阻的对策,推出了一种改进的铆接工艺,能够有效降低、稳定电极箔与引线间的铆接接触电阻。     

片式铝电解电容器的设计与工艺探讨

铝电解电容器的片式化关系着ＳＭＴ技术的进程。片式铝电解电容器设计着眼点在耐焊接热、结构紧凑、性能稳定及长寿命方面。工艺质量控制在铆接、包卷、浸渍、装配、装底座等方面。标准、国产化材料、工艺技术是国内生产片式铝电解电容器尚待解决的问题。     

铝电解电容器开路和假性短路现象分析与改进

导针型铝电解电容器的开路现象主要是因为裂箔、钉接不良、钉接花瓣小、正箔表面箔灰厚及原箔腐蚀太深而造成。假性短路的现象主要是跑片、抽芯、钉花毛刺、导针毛刺、铝箔边缘毛刺、芯子高低脚等原因而造成。只要加强工艺的控制、选用适当的材料可以杜绝铝电解电容器的开路和假性短路现象的发生。     

绿色照明用铝电解电容器的研制

通过合理选用原材料、正确设计零部件、开发高稳定工作电解液、使用负极贴箔技术,配合极片与导针间接触电阻的控制、芯包铝箔粉尘的清除以及浸渍和装配的特殊工艺措施,研制出耐高温、耐大纹波电流、长寿命(130℃,2 000 h或105℃,8 000 h)铝电解电容器,满足高品质绿色照明用产品的要求。     

片式铝电解电容器的设计与工艺设计

铝电解电容顺的片式化关系着ＳＭＴ技术的进程。片式铝电解电容器设计着眼点在耐焊接热，结构紧凑，性能稳定及长寿命方面。工艺质量控制在铆接，包卷，浸渍，装配，装底座方面。标准，国产化材料，工艺技术是国内生产片式铝是解电容器尚待解决的问题。     

铝电解电容器的气体释放

1.电容器中的气体的来源 在铝电解电容器的制造过程中,阳极铝箔上的介质氧化膜不可避免地受到损伤,如切边处、刺铆点处氧化膜被直接破坏。而电容器的老练工艺是对被破坏的氧化膜进行修补和再形成的过程,在阳极铝被氧化的同时,阴极不可避免地要放出氢气。其基本反应式如下:     

铝电解电容器电极箔与引线间接触电阻的改进

铝电解电容器的内部电阻直接影响产品电性能,生产过程中必须降低并稳定电极箔与引线间的接触电阻。通过对铆接过程的分析和研究,提出改进铆接工艺的方法,即采用电极箔预冲孔的铆接工艺。实物测试表明,电极箔与引线间的接触电阻较工艺改进前降低8%～15%,其阻值离散度显著缩小,且后续制造工序及产品使用中的阻值也更稳定,有利于保证产品质量,延长产品寿命。     

CMOS chip for invasive ultrasound imaging

A very small transmit/receiver chip has been developed for use in an arterial ultrasonic imaging system. In this technique, a solid-state ultrasonic imaging head placed within a small medical catheter is used to provide high quality 360° images of arteries as small as 2 mm in diameter. Novel design and packaging techniques have been used to allow four easily testable 0.86 mm×1.65 mm mixed-signal CMOS die to be placed on a multichip carrier within this 1.83 mm diameter imaging probe. Each chip contains interface circuitry for sixteen transducers including 20 MHz transmit pulsers and receive current amplifiers with approximately 1.3 pA/rt-Hz equivalent input noise performance. The techniques described here are generally applicable to any probe or device with extreme size and performance requirements     

一种基于DSP控制的飞机电磁铆枪控制电路设计

设计一种基于DSP控制的飞机电磁铆枪控制电路,依据电磁铆枪在飞机构件铆接过程中的技术要求,设计出充电电压采集电路、充电回路控制电路以及放电回路控制电路.     

Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die

The cost and quality of a multichip assembly is highly dependentupon the cost and quality of the incoming die. In the case of a baredie assembly, it is often highly desirable to use either Known Good Die(KGD) or die that have been burned-in and tested to the same level ofquality and reliability as their packaged die equivalents. However,performing full bare die burn-in and test may not always becost-effective. This paper examines the question of whether it isalways necessary to use KGD to produce a cost-effective multichipmodule (MCM) of acceptable quality. A process-flow based cost modelis used to compare the cost and quality of MCMs assembled with KGD toMCMs assembled with die that have received wafer-level test only. Inaddition to test effectiveness at the wafer, die, and module level,factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, andrework costs and effectiveness. The cost model captures inputs fromwafer fabrication through MCM assembly and rework. Monte Carlosimulation is used to account for uncertainty in the input data.The resulting sensitivity analyses give final MCM cost and quality asa function of the various factors for both KGD and die that havereceived wafer-level test only.     

KGD技术发展与挑战

军用和民用电子系统中模块化和小型化发展的迫切需求使裸芯片在国内有着广泛的用途和市场，尤其是在军用HIC和MCM应用领域，裸芯片质量和可靠性保证一直是人们关注的热点，本文论述了国外KGD技术发展现状，以及国内发展KGD技术面临的机遇与挑战，论述了已知良好芯片（KGD）保证的主要技术要求，重点介绍了KGD夹具技术和工艺流程，为国内KGD技术的发展提供了技术指导。     

Thermal transient characteristics of die attach in high power LED PKG

The reliability of packaged electronics strongly depends on the die attach quality because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED PKG have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated for characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED PKG. From the differential structure function of the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding with the thermal resistance of about 3.5 K/W was much better than this of Ag paste and solder paste with the thermal resistance of about 11.5–14.2 K/W and 4.4–4.6 K/W, respectively. From this results, it is possible to fabricate high power LED with a small thermal resistance and a good die attach quality by applying Au/Sn eutectic bonding die attach with a high reliability and a good repeatability.     

Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.     

The EFG process applied to the growth of silicon ribbons*

The development of edge-defined, film-fed growth (EFG) techniques for silicon ribbons has prompted analyses of appropriate die materials, die shapes, meniscus shapes and thermal gradients. The requirement for high electronic quality of the ribbons, in conjunction with the high effective solute distribution coefficients expected for EFG, narrows the choice of die materials primarily to graphite and fused silica. The shape of the meniscus between crystal and die has been calculated. This shape, together with contact angle information, is used to determine design criteria for both graphite and silica dies. The effect of crystal growth on the temperature gradient ahead of the growth interface has been calculated in terms of the ribbon thickness and an empirical parameter characterizing the radiating environment of the growth apparatus. Numerous 25 mm wide × 0.3 mm thick ribbons from carbon dies and a few small ribbons from silica dies have so far been grown. The ribbon quality is discussed. Work supported by the National Science Foundation.