Modulation of the effective work function of fully-silicided (FUSI) gate stacks

A systematic analysis of the different methods of work function (WF) tuning for gate stacks using fully silicided (FUSI) gate electrodes is presented. We show that FUSI gates have the potential to meet the WF requirements for future nodes, including high performance applications, achieving band edge WF, with total WF range of up to ∼900 meV. The introduction of dopants (such as Sb, As, P, B) by ion implantation is shown to be effective to tune the WF of NiSi or Ni₃Si₂ on SiO₂ or SiON by ∼550 meV, but is ineffective on HfSiON or for Ni-richer silicides. Different silicide phases can be used for Ni FUSI gates on HfSiON dielectrics, taking advantage of the higher WF of metal-rich silicides, achieving a WF range of ∼400 meV. This method is not effective, however, on SiON dielectrics. The introduction of Lanthanides by several techniques (such as dielectric cap deposition, ion implantation into poly-Si, or at metal deposition) that result in the modification of the dielectric, is found, for Ni FUSI gates, to achieve low WF (∼4.0 eV) suitable for NMOS. Similarly, incorporation of Al can be used to achieve PMOS type WF, as well as the use of metal-rich Ni and/or Pt based FUSI gates (with WF as high as 5.0 eV).     

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

Cost-Effective Low Vt Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and Yb+P Coimplant (nMOS)

Low V_t Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the V_t shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low V_t dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-k dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.     

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

We investigated the influences of gate metals (n⁺/p⁺ poly-Si, Ni silicide (NiSi), Ni₃Si) on the time dependent dielectric breakdown (TDDB) reliability and negative/positive bias temperature instability (NBTI/PBTI) of phase-controlled Ni-full-silicide (Ni-FUSI)/HfSiON/SiO ₂ FETs. The TDDB reliability of NiSi-electrode n-FETs was comparable to that of n⁺-poly-Si-electrode n-FETs. However, further Ni enriching of the electrode to Ni₃Si degraded the reliability. A degradation of the base SiO₂ layer seems to have been responsible for this. A higher compressive strain was observed for the Ni₃Si sample, which may have caused the degradation of the bottom SiO₂. In contrast, the TDDB reliability of p-FETs improved much by using Ni₃Si. We attribute this improvement to the lower cathode energy and/or the absence of boron in the gate electrode. The PBTI of the n-FETs was negligible and was not degraded by Ni enrichment of the gate electrode and additional annealing, suggesting that HfSiON was stable against the Ni-FUSI process. The threshold voltage (V_T) shift in NBTI of p-FETs did not depend much on the gate materials. The major component of the V _T shift in NBTI, however, was changed by Ni enriching from the generation of interface traps to the trapping of holes by the HfSiON bulk     

Dual work function metal gates using full nickel silicidation of doped poly-Si

This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi-SiO/sub 2/ interface. No degradations on the underlying gate dielectrics are observed in terms of interface state density (D/sub it/), fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing.     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode

In this letter, nMOSFETs using a NiSi:Yb fully silicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NiSi:Yb FUSI into our reference n-FETs with the respective SiON / HfSiON gate dielectrics results in a V_t reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel device mobility     

A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the Ni_xSi FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance I_ON. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the I_ON of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data     

SiC MOSFETs with thermally oxidized Ta2Si stacked on SiO2 as high-k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta₂Si (O-Ta₂Si) as a high-k dielectric on silicon carbide or stacked on thermally grown SiO₂ on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO₂/O-Ta₂Si is an attractive solution for passivation of innovative SiC devices. Ta₂Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta₂Si on thin thermally grown SiO₂ oxides. However the channel mobility of such high-k MOSFETs must be improved investigating the interface properties further.     

Work function tuning of fully silicided NiSi metal gates using a TiN capping layer

This paper investigates a new way of tuning the work function of fully silicided (FUSI) NiSi metal gates for dual-gate CMOS using a TiN capping layer on Ni to control the poly-Si dopant distribution during FUSI formation. In addition, by comparing the work function change of NiSi FUSI with and without TiN capping, we provide clear evidence that dopants at the gate electrode and dielectric interface are responsible for the work function change. The TiN capping layer causes no degradation to the underlying gate dielectric in terms of fixed-oxide charge, gate leakage current, and time-dependent dielectric breakdown characteristics.     

Investigation of poly-Si1-xGex for dual-gateCMOS technology

Poly-Si_1-xGe_x-gated MOS capacitors were fabricated with x varying from 0 to 0.5. NMOS and PMOS C-V characteristics were measured. Reduced poly-gate depletion effect (PDE) was observed in PMOS devices with increasing Ge mole fraction; while for NMOS, devices with a Ge content ~20% exhibit the least PDE. Higher active dopant concentration and reduced gate-depletion width for devices featuring less PDE were confirmed. Work function difference (Φ_MS) was found to decrease slightly in N⁺ films and significantly in P⁺ films as Ge content increases. The shift in Φ_MS for N⁺ poly-Si_1-xGe_x is negligible while it is -0.13 V for P⁺Si_0.8Ge_0.2 and -0.32 V for P⁺Si_0.5Ge_0.5. The reduction in energy bandgap (ΔE_g) was also determined to increase from 0 to 0.26 eV as Ge content increases from 0 to 50%. For deep submicron dual-gate CMOS application, the shift in Φ_MS should be minimized for low and symmetrical V_th as well as improved short-channel effect (SCE). A Ge content of ~20% therefore seems to offer the best tradeoff between SCE and PDE     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Linewidth effect and phase control in Ni fully silicided gates

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni/sub 2/Si, and Ni/sub 31/Si/sub 12/. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V/sub t/ control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni/sub 2/Si processes with excessive thermal budgets, resulting in significant V/sub t/ shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V/sub t/ rolloff characteristics was demonstrated for NiSi, Ni/sub 2/Si, and Ni/sub 31/Si/sub 12/ FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni/sub 2/Si are less than or equal to 25 /spl deg/C, whereas a single-phase Ni/sub 31/Si/sub 12/ is obtained over an /spl sim/200/spl deg/C temperature range.     

Observation of reduced boron penetration and gate depletion forpoly-Si0.8Ge0.2 gated PMOS devices

Poly-Si_0.8Ge_0.2-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si _0.8Ge_0.2-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO₂ interface and therefore improved PDE were also found in boron-implanted poly-Si_0.8Ge_0.2-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si_0.8Ge_0.2 gate technology with regard to the tradeoff between boron penetration and poly-gate depletion     

Modulation of the workfunction of Ni fully silicided gates by doping: dielectric and silicide phase effects

A systematic study of the modulation of the workfunction (WF) of Ni fully silicided gates by doping is presented, comparing the effects of dopants (Al, B, undoped, P, and As) on the WF for different dielectrics (SiO/sub 2/ versus HfSiON) and silicide phases (NiSi, Ni/sub 2/Si and Ni/sub 31/Si/sub 12/). Dual thickness series (HfSiON/SiO/sub 2/) were used to extract accurate WF values accounting for charge effects on HfSiON. While a WF modulation in the range of /spl sim/0.4 V was obtained for NiSi on SiO/sub 2/ comparing As, P, and B doped and undoped devices, negligible modulation was obtained for NiSi on HfSiON (/spl les/50 mV) suggesting Fermi-level pinning, and for the Ni-rich silicides on SiO/sub 2/ (/spl les/100 mV). Dopant pileup at the dielectric interface, believed to be responsible for the NiSi/SiO/sub 2/ WF modulation, was, however, observed for both NiSi and Ni-rich silicides. In contrast the WF of Ni-rich silicides on SiO/sub 2/ can be modulated with Al, suggesting a different mechanism of WF tuning for Al compared to B, P, and As.     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects     

Impact of Gate Electrodes on $hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors

The low-frequency (1/f) noise of gate-all-around silicon nanowire transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region. It shows that the gate electrodes have a strong impact on the 1/f noise of the SNWTs. The highest noise is observed in the SNWTs with a poly-Si gate, compared to their FUSI-gate counterparts. The observations are explained according to the number fluctuation with correlated mobility fluctuation theory by assuming that the correlated mobility scattering is better screened in the case of an undoped FUSI gate. However, the doped FUSI gate with silicidation-induced impurity segregation at the gate/SiO₂ interface gives rise to extra mobility scattering.