Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Heating effects of clock drivers in bulk, SOI, and 3-D CMOS

Steady-state and transient thermal behavior of the highest power density element in systems and chips-the clock driver-in bulk, silicon-on-insulator (SOI), and three-dimensional (3-D) CMOS is examined. Despite significant metal wiring, a majority of the heat conducts through the buried oxide (BOX) in SOI and the buried interconnect layer in 3-D CMOS. 3-D CMOS has the potential to improve substantially over SOI CMOS in thermal behavior by increasing the wiring density directly beneath the clock driver. Temperature mismatch (important for analog applications) between device planes in 3-D CMOS occurs within a characteristic length, which is as large as 13 /spl mu/m for clock drivers. These results suggest advantages and architectural options for the design of high-power devices in 3-D integration.     

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-/spl mu/m and 0.25-/spl mu/m CMOS with different pixels array sizes. For 2-/spl mu/m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-/spl mu/m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.     

SOI for digital CMOS VLSI: design considerations and advances

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues     

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

Comparison of SOI and junction isolation for substrate crosstalksuppression in mixed mode integrated circuits

Using two-dimensional computer simulations and measurements on silicon, it is shown that whereas silicon-on-insulator (SOI) based processes provide high isolation from crosstalk in mixed mode analogue-digital integrated circuits, p-i-n junction isolation can provide equal or better crosstalk immunity with less expense     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

Monolithic CMOS digital integrated circuits in 6H-SiC using animplanted p-well process

We report the first p-well Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits in 6H-SiC. Enhancement mode NMOSFET's and PMOSFET's are fabricated on implanted p-wells and n-type epilayers, respectively. CMOS logic circuits such as inverters, NAND, NOR, XOR, flip-flops, half adders, and 11-stage ring oscillators are implemented using these devices and operated at room temperature, The inverters show stable operation at room temperature and 300°C with V_dd=10 and 15 V     

Performance limits of mixed analog/digital circuits with scaledMOSFETs

Constant electric field (CE), quasi-constant voltage (QCV), and constant voltage (CV) scaling laws are used as guides to MOSFET miniaturization. It is found that: 1) the QCV scaling law gives the best performance of the three scaling laws; 2) improvements in unity-gain bandwidth with scaling are less than predicted by the first-order theory due to mobility degradation; 3) gate length can be scaled down to 0.25 μm while maintaining 10-bit accuracy for analog circuits (threshold variation limit); and 4) when gate lengths deviate from designed values, noise immunity for digital circuits is degraded mainly due to degradation in the saturation characteristics (drain-induced barrier lowering)     

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

Analysis of crosstalk interference in CMOS integrated circuits

The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated     

数模混合集成电路版图设计的涨缩技术

文章介绍了在数模混合版图设计中,如何把版图不同模块的涨缩需求,用一种完善的自动化程序技术方案来实现,并且可以批处理所有需要涨缩的版图数据。     

The influence of design and process parameters on the reliability of CMOS integrated circuits

As system reliability becomes increasingly dependent on integrated circuit reliability it is essential to achieve high reliability at low cost. In this paper we will discuss the reliability of CMOS I.C.'s. Design and manufacturing considerations which are used to build reliability into the product will be discussed. Industry standard accelerated life testing was used to evaluate the product in epoxy packages.     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS     

Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.