Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Differential thermal budget in laser processing: application toformation of titanium silicide

One of the crucial issues that must be faced when using titanium silicide in advanced IC structures is the difficulty encountered in phase transforming the silicide from the its high to its low resistivity phase. As gate dimensions are reduced there is a reduction in the number of nucleation sites available to initiate transformation on laterally and vertically confined films. In this letter, we demonstrate a novel technique, using a pulsed excimer laser, to produce thicker silicides over the gate than over the source and drain regions. This is difficult to achieve using conventional thermal processing. The increased thickness of silicide over the gate region should assist in alleviating the phase transformation problem     

Selective deposition of TiSi2 on oxide patterned wafers using low pressure chemical vapor deposition

The selective deposition of titanium disilicide was investigated using a cold-wall, low pressure chemical vapor deposition (LPCVD) technique with silane and titanium tetrachloride as the silicon and titanium sources, respectively. In-situ hydrogen plasma effectively cleaned the silicon wafer surface for deposition of C54 TiSi₂ at 760‡ C with full selectivity. A new method using a plasma only at the beginning of the deposition of the silicide further decreased the temperature to 680‡ C without losing selectivity. The result was a fine grained film probably due to the enhanced nucleation rate of the silicide. Cross-sectional TEM studies showed that the silicide grew into the silicon substrate, suggesting significant silicon consumption. The silicon substrate, consequently, seems to play a major role in the silicide formation. Silane, on the other hand, plays a minor role as a silicon source but does act as a scavenger of HC1 in the gas or on the silicide surface.     

气体流量比对PECVD硅化钛薄膜性质的影响

本文报道了以四氯化钛(TiCl_4)和硅烷(SiH_4)为源物质,采用等离子增强化学气相淀积工艺(PECVD)制备硅化钛薄膜的方法;着重研究了气体流量比变化对薄膜电阻率、淀积速率以及化学组成的影响,通过实验获得了制备优良硅化钛薄膜的最佳气流比条件。     

PECVD法制备硅化钛膜的工艺研究

硅化钛薄膜由于电阻率低和其它一些良好特性,在VLSI的栅电极和互连线中显示出它潜在的优势。本文研究了用PECVD法制备硅化钛膜的卫艺。结果表明:所形成硅化钛膜的性质强烈地依赖于淀积工艺条件。还确定了典型工艺条件,并用俄歇电子能谱分析了硅化钛膜的组分。     

Formation of titanium silicide on narrow gates using laser thermalprocessing

One of the crucial issues that must be faced when using titanium silicide in advanced IC structures is the difficulty encountered in transforming the silicide from its high to its low resistivity phase. As gate dimensions are reduced, there is a reduction in the number of nucleation sites available to initiate transformation on laterally and vertically confined films. In this paper we demonstrate a novel technique, using a pulsed excimer laser, to produce thicker silicides over the gate than over the source and drain regions. This is difficult to achieve using conventional thermal processing. The increased thickness of silicide over the gate region assists in alleviating the phase transformation constraints. In this paper, we demonstrate fabrication of low resistivity salicide on gate lengths as small as 0.07 μm. We also demonstrate, through the use of two-dimensional thermal simulations, the use of amorphization as a method for overcoming the barriers to integration of laser thermal processing in conventional MOSFET fabrication     

Titanium silicide-silicon interface degradation during heat treatment

Thin titanium silicide films were grown on different silicon substrates by rapid thermal annealing in a nitrogen ambient. The silicide films were then annealed in a furnace at high temperature in a nitrogen ambient for various times. The effect of such heat treat-ment on the morphology of titanium silicide surface and the titanium silicide-silicon interface was studied. It is proposed that the morphological change is primarily due to the diffusion of silicon and/or dopant impurities via grain boundaries of the silicide. There is a strong correlation between the surface of the titanium silicide film and that of the titanium silicide-silicon interface.     

Effect of rapid thermally nitrided titanium films contacting silicided and nonsilicided junctions

The effect of rapid thermally nitrided titanium films contacting silicided (titanium disilicided) and nonsilicided junctions has been studied in the temperature range of 800 to 900°C. The rapid thermal nitridation of titanium films used as diffusion barriers between aluminum and silicon, has a major impact on shallow junction complementary metal oxide semiconductor technologies. During the process of rapid thermal nitridation, the dopants in the junctions undergo a redistribution and affect the electrical properties of shallow junction structures. This work focuses on using novel contact resistance structures to measure the variation in electrical parameters for rapid thermally nitrided titanium films annealed at different temperatures. The self-aligned silicide (salicide) junctions in this study were formed using rapid thermally annealed titanium films. Electrical contact resistance testers were used to measure the interface contact resistance between the salicide and silicon, as well as between the metal and the salicide. The results show that the interface contact resistance to the p⁻ diffused salicided junctions increases with rapid thermal nitridation of the additional titanium film, whereas the interface contact resistance to the n⁻ diffused salicided junction shows a decrease. Further, as a function of the rapid thermal annealing temperature (for fixed titanium thickness), the nonsalicided diffusions show an increase in the interface contact resistance. The boron profiles at the TiSi₂/Si interface obtained using secondary ion mass spectroscopy show an excellent qualitative agreement with the electrical results for each of the conditions discussed. The films were also characterized using Rutherford back-scattering spectrometry and transmission electron microscopy and the results show good agreement with the measured variation in electrical parameters. These results also show that as the anneal temperature is increased, the TiN thickness increases, further the change in the silicide/silicon interface position with the nitridation of the additional titanium layer was verified. This work was carried out when the author was working at AT&T Bell Labs     

Characteristics of DC magnetron sputtered ternary cobalt-nickel silicide thin films for ultra shallow junction devices

Ternary cobalt-nickel silicide thin films were synthesized by DC magnetron sputtering from an equiatomic cobalt-nickel alloy target. Grazing incidence XRD, Rutherford back scattering, high-resolution cross-sectional TEM analysis and electrical study were carried out to investigate the formation of silicide, stoichiometry, film thickness, depth profile and sheet resistance of as-deposited and post-deposition annealed films. The ternary silicide layer thickness was calculated from RBS simulated data, which was found to vary 20-43 nm for as-deposited and different vacuum annealed films. A minimum value of sheet resistance 2.73 Ω/sq corresponding to a resistivity of ∼8.4 μΩ-cm was obtained for optimized deposition and annealing conditions.     

The oxidation of titanium silicide

This paper investigates the morphology changes that occur with the oxidation of a ti-tanium silicide—polysilicon system. These changes were studied as a function of poly-silicon doping and silicide formation parameters. Emphasis was placed on transmission electron microscopy studies of the samples by planar and cross sectional techniques. Various surface analysis methods have also been used to characterize the films. This study helps to define the possible use and shortcomings of a self aligned titanium silicide insulator. The results show that varying quality insulators result, dependent largely on the initial conditions of the titanium silicide. After oxidation the Auger and TEM anal-ysis show that in all cases some form of silicon dioxide was created, but typically a considerable amount of titanium oxide was also present. For instance, it was apparent that more titanium oxide formed on the samples RTA’ed for 1 min at 700° C than the 5 min at 800° C and considerably more on the arsenic doped sample than the boron doped. The silicide also had morphology changes as the result of the oxidation. There was a phase change from the C49 to C54 phase for the 1 min at 700° C samples as would be expected at the time and temperature of the oxidation. There also was a sig-nificant amount of agglomeration and epitaxial growth observed. Further work is re-quired to completely characterize these phenomena.     

The process window of a-Si/Ti bilayer metallization for anoxidation-resistant and self-aligned TiSi2 process

The dependences of both oxidation-resistant and self-aligned silicidation properties on the thicknesses of top amorphous-Si (a-Si) and Ti metal in an a-Si/Ti bilayer process are presented. It is shown that a thin silicide layer formed during the reaction between a-Si and Ti films becomes a stable oxidation and nitridation barrier for oxygen- and nitrogen-related impurities. Moreover, the formation sequence of the silicide phase depends not only on the annealing temperature but also on the thickness of the Ti film. In addition, the preferential orientation of the silicide phase after annealing at high temperature also shows a strong dependence on the thickness of Ti film, which is attributed to the difference of the grain size in the polycrystalline silicide film. The allowed process window for the a-Si thickness can be determined experimentally and a reproducible and homogeneous self-aligned TiSi₂ film can be easily obtained by using the a-Si/Ti bilayer process in salicide applications despite high-level contaminations of oxygen impurities in both the as-deposited Ti film and the annealing ambient     

Measurement and control of a residual oxide layer on TiSi2 films employed in ohmic contact structures

An inadvertent oxide layer is formed on a titanium disilicide (TiSi₂) film following various wet and dry processes in a manufacturing environment. The use of H₂SO₄:H₂O₂:H₂O (1:1:5) as a wet etch for excess Ti metal, prior to the high temperature anneal used to form a subsequent TiSi₂ layer, is identified as the source of the undesired oxide via multiwavelength spectroscopic ellipsometry and Auger electron spectrometry studies. This inadvertent oxide layer on TiSi₂ is shown to form bad electrical contacts and is a contributing source to large standby currents in polysilicon gate shunts. Spectroscopic ellipsometry is shown herein as a unique analytical tool to determine both the thickness and structure of this poorly structured oxide during process development. A single wavelength ellipsometer monitoring scheme for both the appearance as well as the thickness of this inadvertent oxide layer is proposed for use in high-volume manufacturing     

亚微米CMOS IC中自对准硅化物工艺的研究

自对准硅化钛工艺有许多重要的优点.但也存在栅氧化物的完整性、硅化物桥接短路、pn结损伤、二极管特性退化等问题.文章针对这些问题,在硅化前和硅化后的清洗、硅化的快速退火处理、接触电阻最佳化以及在硅化物上的接触孔腐蚀的选择性等方面进行了改进,有效地解决了问题.     

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

PET复合衬底上梯度介质薄膜厚度的椭偏表征

为了监控3维玻璃上聚对苯二甲酸乙二醇酯(PET)复合衬底介质膜膜厚, 采用将PET复合衬底等效为单层基底材料的建模分析方法, 通过椭偏测量技术实现了复杂衬底上TiO₂梯度折射率材料薄膜厚度的检测。结果表明, 采用该方法测量的PET复合衬底上TiO₂梯度折射率薄膜厚度为212.48nm, 扫描电子显微镜的测量结果为211nm, 结果非常准确。以TiO₂为例验证了等效衬底方法, 该方法也同样适用于其它介质膜。等效衬底法可实现PET复合衬底上的TiO₂薄膜厚度的高精度测量表征, 对镀膜工艺过程监控具有重要意义。     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

氢化非晶硅薄膜的性能研究

本文研究了PECVD系统沉积薄膜及其特性．通过椭偏仪测出了薄膜的膜厚, 采用电子薄膜应力分布测试仪分析了薄膜应力,并运用四探针装置研究了电阻率、方阻、TCR及它们之间的相互关系。结果表明,所沉积的薄膜覆形特性好、沉积速度快, 沉积速率达到了31．89nm／min,另外,它还具有低应力、高TCR的特点;当薄膜电阻率处在一定的范围内时,通过数据分析,电阻率与TCR之间几乎成线性关系．     

Two-dimensional effects in titanium silicidation

New experimental results are reported on the two-dimensional (2-D) effects associated with titanium silicidation on small and nonuniform structures. Based on a unique set of test structures, new insight into the silicidation process is obtained. Small geometry by itself does not seem to be restraining silicide formation. Thick silicide is demonstrated to form on the vertical surface of silicon posts of 1000 Å radius and on top of 1200 Å wide silicon lines. Also discussed are the possible roles of mechanical stress and the Si-SiO₂ interface in the 2-D silicidation and diffusion processes. The original data presented here will be useful in further analysis and simulation of 2-D silicidation process     

TiSi_2薄膜的形成特性及TiSi_2/多晶硅复合栅结构的研究

本文用反应生成和合金靶溅射两种方法生成了TiSi_2薄膜,并对其形成特性进行了研究,同时将所形成的TiSi_(?)薄膜应用于MOSFET和MOS电容的制作中.结合电学性反的测量和TEM(横截面)在位观察,研究了TiSi_2/多晶硅复合栅结构的特性,发现当多晶硅厚度小于某一临界值时,经高温炉退火后,SiO_2/Si界面将会产生许多新的界面在,SiO_(?)层中会产生缺陷.对离于注入和热扩散掺杂的两种样品,多晶硅层厚度的这个临界值几乎是相同的.根据我们的实验和分析结果,证实了在TiSi_2薄膜的形成过程中所引入的应力是产生上述现象的基本原因.