一种瞬态增强无片外电容LDO电路

基于CSMC 0.18 μm工艺,设计了一款瞬态增强的无片外电容LDO。设计误差放大器时,采用改进的第2级放大器提高功率管栅端的充放电速度,从而提高瞬态响应。采用嵌套密勒补偿方式来保证LDO的稳定性。仿真结果表明,输入电压为2~4.5 V时,LDO的输出电压为1.8 V,负载电流在1~300 mA之间具有良好的稳定性,响应时间为1.4 μs,最大过冲电压为84 mV。     

无输出电容的瞬态增强NMOS LDO

提出了一种用于片内数字驱动的瞬态增强NMOS低压差线性稳压器(LDO)。该LDO采用电容耦合动态偏置和双环路推挽式驱动调整管,极大地提高了电路的瞬态响应速度。基于0.35 μm BCD工艺的仿真结果表明,负载电流在0.1~100 mA之间的跃迁时间为100 ns时,电路的下冲电压为42 mV,过冲电压为66 mV,稳定时间仅为323 ns。该LDO电路的总体静态电流约为50 μA,输出电流最大值为100 mA。     

一种缓冲器阻抗动态调整的LDO

提出了一种缓冲器阻抗动态调整的LDO结构。采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响。该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能。基于TSMC 0.18 μm 3.3 V CMOS工艺进行设计,该LDO的输出电压为1.8 V,压差电压为0.2 V,最大输出电流为100 mA。仿真结果显示,LDO的静态电流只有5 μA,当负载电流在10 ns内从0 mA跳变到100 mA时,输出欠冲和过冲电压分别为88.2 mV和34.8 mV。     

一种具有瞬态增强的无片外电容型LDO

提出了一种稳定性高、瞬态特性良好、无片外电容的低压差线性稳压器(LDO)。采用推挽式微分器检测负载瞬态变化引起的输出电压变化,加大对功率管栅极寄生电容的充放电电流,增强系统的瞬态响应能力;在误差放大器后接入缓冲级,将功率管栅极极点推向高频,并采用密勒电容进行频率补偿,使系统在全负载范围内稳定。基于TSMC 65 nm CMOS工艺进行流片,核心电路面积为0.035 mm²。测试结果表明,最低供电电压为1.1 V时,压降仅为100 mV,负载电流1 μs内在1 mA和150 mA之间跳变时,LDO的最大输出过冲电压与下冲电压分别为200 mV和180 mV。     

一种无片外电容高瞬态响应LDO设计

针对SoC中电源管理模块对高功能-面积比和高瞬态响应的需求,本文提出一种基于翻转电压跟随器（FVF）的无片外电容低压差线性稳压器（LDO）,采用电压峰值检测技术实现动态电流偏置,进而提升系统瞬态响应。基于SMIC 40nm工艺的仿真结果表明,在典型负载切换状态下,提出方案的下冲和上冲恢复时间相比传统的FVF结构LDO电路分别缩短了75%和29%。     

一种快速瞬态响应无片外电容LDO

针对无片外电容LDO,在误差放大器与功率管之间添加缓冲器,采用频率补偿的方法,提高了环路稳定性。通过检测负载瞬态变化引起的误差放大器输出电压变化,增加对功率管栅极电容的充放电电流,提升了系统的快速瞬态响应能力。基于TSMC 0.18 μm标准CMOS工艺,设计了一种输入电压范围为1.92~3.60 V、输出电压为1.8 V的LDO。结果表明,负载在1 μs内从0变化到100 mA时,输出最大下冲电压为37.2 mV,响应时间为1.12 μs;负载在1 μs内从100 mA变化到0时,输出最大过冲电压为40.1 mV,响应时间为1.1 μs。     

一种低功耗无片外电容LDO的设计

基于SMIC 0.18 μm CMOS工艺,设计了一款输入电压为1.8 V、输出电压为1.6 V的低功耗无片外电容低压差线性稳压器(LDO),其静态电流仅为5 μA。该电路采用一种新型摆率增强电路,通过检测输出电压的变化实现对功率管的瞬态调节。片内采用密勒补偿使主次极点分离,整个系统在负载范围内具有良好的稳定性。仿真结果显示,该LDO在负载电流以99 mA/1 μs跳变时,输出电压下冲为59 mV,上冲为60 mV,响应时间约为1.7 μs。     

一种无片外电容LDO的瞬态增强电路设计

利用RC高通电路的思想,针对LDO提出了一种新的瞬态增强电路结构。该电路设计有效地加快了LDO的瞬态响应速度,而且瞬态增强电路工作的过程中,系统的功耗并没有增加。此LDO芯片设计采用SMIC公司的0.18μmCMOS混合信号工艺。仿真结果表明:整个LDO是静态电流为3.2μA;相位裕度保持在90.19°以上;在电源电压为1.8 V,输出电压为1.3 V的情况下,当负载电流在10 ns内由100 mA降到50 mA时,其建立时间由原来的和28μs减少到8μs;而在负载电流为100 mA的条件下,电源电压在10 ns内,由1.8 V跳变到2.3 V时,输出电压的建立时间由47μs降低为15μs。     

一种采用电压检测器的无片外电容FVF-LDO

提出了一种基于翻转电压跟随器(FVF)的无片外电容低压差线性稳压器(LDO)。采用电压检测器来检测输出电压,大幅改善了瞬态响应,克服了常规LDO面积大、需要使用片内大电容的缺点,仅消耗了额外的静态电流。该LDO采用90 nm CMOS工艺进行设计与仿真,面积为0.009 6 mm²,输入电压为1.2 V,压差为200 mV。结果表明,在50 pF负载电容、3～100 mA负载电流、300 ns跃迁时间的条件下,产生的上冲电压为65 mV,瞬态恢复时间为1 μs,产生下冲电压为89 mV,瞬态恢复时间为1.4 μs,且将负载调整率性能改善到0.02 mV/mA。     

一种低静态电流高瞬态响应无片外电容LDO设计

基于SMIC 0.18μm BCD工艺设计了一种低静态电流、高瞬态响应的无片外电容低压差线性稳压器(Low Dropout Regulator, LDO)。误差放大器采用一种跨导提升技术,在低静态电流的情况下,实现更高的环路增益及单位增益带宽。由于采用高增益误差放大器,可以通过适当减少功率管尺寸来增强瞬态响应。采用有源反馈,在不引入额外静态电流情况下,增大环路的次极点。同时当LDO输出电压变化时,能够增大功率管栅极的动态电流,实现高瞬态响应。此外在有源反馈的基础上,采用反馈电阻并联小电容的方式,以提高环路稳定性。利用Cadence Spectre软件对LDO进行仿真验证。结果显示,LDO的静态电流仅为10μA;在负载电流为1 mA的情况下,相位裕度最高可达70.9°;LDO负载电流在500 ns内从1 mA切换到100 mA时,下冲电压为134.7 mV,下冲电压恢复时间为1μs;负载电流在500 ns内从100 mA切换到1 mA时,过冲电压为155.5 mV,过冲电压恢复时间为430 ns。     

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90 nm CMOS process is only 0.054 mm². Experimental results show that the developed LDO can supply up to 15 mA and it presents a very fast transient response, with a settling time of approximately 30 ns and a voltage drop of 200 mV when the load current changes from 100 nA to 9 mA.     

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18 μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7 μs and the maximum undershoot and overshoot are as low as 55 mV and 30 mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37 mV/V and 2 μV/mA, respectively.     

A wide-bandwidth PSR-enhanced low-dropout regulator using a bandpass feedforward supply ripple rejection circuit

A low-dropout regulator with a wide-bandwidth feedforward supply noise cancellation path for enhancing supply noise rejection at middle-to-high frequency is presented in this paper. This idea has been realized by a bandpass filter and a signal-nulling technique with the help of a voltage buffer. For the PSR filter design, the total on-chip capacitance is about 18.75 pF. This circuit has been implemented in a 0.35 µm CMOS process and occupies an active chip area of 0.062 mm². From the experimental results, the proposed LDO can operate with nominal dropout voltage of 200 mV at maximum load of 25 mA and quiescent current of 26 μA. It achieves a power-supply rejection better than ?59 dB up to 10 MHz with a 4 μF output capacitor.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

Sleep-mode ready,area efficient capacitor-free low-dropout regulator with input current-differencing

This paper proposes an input current-differencing technique in designing a capacitor-free low-dropout regulator to simultaneously achieve sleep-mode efficiency and silicon real estate saving. With no minimum output current required to be stable, the regulator could greatly improve SoC efficiency during standby, which is extremely attractive for battery powered applications. Designed in TSMC 0.18-μm CMOS technology, it regulates 1.8–1.2 V supply down to 1 V with 100 mA maximum output current and can drive up to 100 pF of load parasitic capacitance. Compared with prior arts with the same sleep-mode compatibility and similar output current range, it reduces the on-chip compensation capacitance from 21 to 4.5 pF.     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6-/spl mu/m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%.