Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.     

A novel EER structure for reducing complexity using negative resistance amplifier

This letter presents a novel envelope elimination and restoration (EER) structure using the negative resistance class F power amplifier. Due to the extremely high gain characteristic of the negative resistance amplifier in very narrow bandwidth, it operates in saturation mode. This characteristic is applied to the proposed EER. Using this technique, a limiter, a drive amplifier, and a class F power amplifier in conventional EER can be substituted with the negative resistance class F power amplifier. This technique greatly reduces the complexity of conventional EER without degradation of efficiency and linearity. The measured results show efficiency of 60% and less than-26 dBc IMD levels for two-tone test in PCS band at 27-dBm output power.     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

An MMAC C-band FET feedback power amplifier

A feedback power amplifier using miniaturized microwave active circuit (MMAC) technology was developed for satellite C-band applications. This design demonstrates that a strong negative feedback can be implemented in the microwave frequencies to improve amplifier linearity and output power over a 750 MHz bandwidth. The amplifier provides a third-order intermodulation distortion improvement of 7 to 9 dB across the band at backoff, compared to results obtained using the conventional approach without feedback. The theory, proof-of-concept experiment, design, and MMAC implementation of the feedback amplifier are presented     

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.     

On a new topology for the transconductance feedback amplifier

A new topology for a transconductance feedback amplifier (TFA) is presented in this paper. The topology offers the advantage that it is capable of realizing the negative of the standard inverting gain expression. That is, gains of the form +R/sub 2//R/sub 1/. We will also show that it can realize the standard inverting and noninverting gains, all the while maintaining near constant bandwidth in each configuration as gain is varied. This first feature makes the proposed topology attractive for filtering applications since the TFA can function as an integrator, thereby allowing this amplifier to realize positive and negative lossless integrators. The proposed amplifier can also generate the logarithm of an input in the first and fourth quadrants, unlike previous TFA configurations. The proposed amplifier was verified experimentally for different gain configurations, integration and logarithmic capabilities by a chip designed using TSMC's 0.18-/spl mu/m CMOS process of a single ended power supply of 1.8 V. The chip occupied an area of 752.6 /spl mu/m by 581.2 /spl mu/m and contained the proposed amplifier and a conventional TFA for comparison purposes. A bandwidth of 15 MHz was observed for the proposed TFA in the unity gain (/spl plusmn/1) configuration.     

适合容性负载的高压大功率放大器

设计了一种适合压电陶瓷等容性负载的双极性可调高压大功率线性放大器,它由简单低廉的低压运算放大器、基于功率场效应管(MOSFET)的功率放大级组成主回路,通过电压负反馈构成闭环控制。对电路中各环节的特性进行了分析,并讨论了放大器的性能。该高压放大器在驱动等效电容为60nF的压电陶瓷时,单端到地输出电压为一600～ 600V,电压增益42dB,大信号带宽800Hz,小信号带宽7kHz,充放电电流可达200mA,静态电流可达1．4mA。实验与分析表明,高压直流放大器采用功率场效应管和电压闭环控制后,可拓展放大器通频带,提高放大器输出能力和长时间稳定性。     

HEMT-HBT matrix amplifier

A novel matrix amplifier using simultaneously high electron-mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) is proposed in this paper. The amplifier includes HEMTs in the first tier and HBTs in the second tier. The HEMT-HBT matrix amplifier in comparison to the HEMT matrix amplifier presents a notable lower dc power consumption without remarkable gain and bandwidth reduction, maintaining the advantage of using HEMTs in the first tier. A theory to demonstrate that the amplifier performance can be optimized if the HBTs in the second tier are properly chosen is also proposed. A comparison among the HEMT-HBT matrix amplifier, HEMT matrix amplifier, and HBT matrix amplifier is also presented     

A new diode-based curve-fitting predistortion lineariser for GaN power amplifier

In this article, a new strategy is presented for selecting the breakpoints on a typical characteristic of a lineariser for a saturating nonlinear amplifier. As a proof of concept, using this strategy, a new Schottky-diode based curve-fitting predistortion lineariser for a 1.65?GHz centre frequency, 50?MHz bandwidth, 30?W GaN power amplifier is developed. The proposed lineariser is tested using the two-tone test and the Quadrature Phase-Shift Keying (QPSK) modulated signal. The results show that a 3?dB improvement in the overall gain of the linearised amplifier is achieved. Moreover, for output power levels up to 36?dBm, the linearised power amplifier provides better rejection of the third-order intermodulation. Because of the hard nonlinearity of the GaN power amplifier at the high end, this improvement in intermodulation rejection vanishes for output power levels around 41?dBm.     

Design for Stability of High-Speed Integrated Photoreceivers: A Tutorial

We propose a Design for Stability (DFS) methodology dedicated to the design of reliable high-speed integrated photoreceiver front-ends. This methodology based on the stability factor, S-parameters and Z-parameters analysis is made of four rules that high-speed designers will apply during the stability check of their design. To demonstrate its effectiveness, the proposed DFS methodology was applied to build a transimpedance amplifier (TIA) compliant to Synchronous Optical Network (SONET) OC-192 (10-Gb/s) standard. Experimental results in agreement with initial design specifications show excellent performances such as: 11 GHz bandwidth, −20 dBm sensitivity measured at 10-Gb/s for a Bit Error Rate (BER) of 10^{− 9} and 10 ps peak-to-peak jitter.     

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

A new technique for designing uniform multistage amplifiers (MAs) for high-frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. The intrinsic capacitances within transistors are exploited by the active negative feedbacks to expand the bandwidth. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Using the proposed topology, a six-stage amplifier in TSMC 0.35-mum CMOS process was designed. Measurement results show that the gain can be varied between 16 and 44 dB within 0.7-3.2-GHz bandwidth with less than 5.2-nV /radicHz noise. Die area of the amplifier is 175 mum times 300 mum.     

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm². The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV V_DO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.     

High-power 10%-tuning-bandwidth varactor-controlled impatt oscillator/amplifier

A simple electronically tuned c.w. GaAs impatt/varactordiode oscillator/amplifier circuit is described which can be tuned over a 10% bandwidth at mid-X-band frequencies at a power level greater than 0.5 W as an oscillator, and greater than 0.8 W at the 6 dB-gain level as a reflection amplifier. Unambiguous electronic tuning without power jumps, frequency hops or `out-of-band? oscillations has been achieved by paying special attention to the circuit design.     

Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation

We present the development of a device-level linearization technique and its applications in broadband power amplifiers (PAs). The proposed topology firstly combines derivative transconductance superposition method and gate capacitance compensation technique, and creates a "sweet region" for suppressing third-order intermodulation (IM3) without the penalty of large power consumption. The effectiveness of the proposed technique has been demonstrated through a fully integrated distributed amplifier. The experimental results in 0.18-mum RF CMOS technology show that IM3 is improved by 11 dB. The achievable power-added efficiency is up to 25%, which is the highest among the broadband CMOS PAs reported thus far. The amplifier achieves a measured 3-dB bandwidth of 3.7-8.8 GHz, and a gain of 8.24 dB. The amplifier only consumes 154-mW dc power, and the measured saturation power (P_sat) is 19 dBm.     

A new simultaneous noise and input power matching technique formonolithic LNA's using cascode feedback

In this paper, a new simultaneous impedance-matching technique of Γ_opt (optimum noise-match source reflection coefficient) and G_max (maximum available power gain-match (MAPG) source reflection coefficient) using cascode feedback (CF) is proposed. A 1.57-GHz single-stage monolithic-microwave Integrated-circuit (MMIC) low-noise amplifier (LNA) designed with this technique has been fabricated using GaAs MESFET technology in order to verify the feasibility of this scheme. The measured response agrees well with the simulated performance. Extensive computer simulation shows that when silicon npn bipolar junction transistor (BJT) is used, this scheme enables us to make both Γ_opt and G_max points near to 50 Ω, in addition to the simultaneous noise and input power matching. In addition, it has all the advantages of negative feedback such as stability, wider bandwidth, and insensitivity against parameter variation     

象限探测器放大组件带宽设计方法研究

为了提高激光导引头探测灵敏度,采用数值仿真的方式,拟合出了象限探测器放大组件带宽与激光导引头探测灵敏度的关系曲线,并定量分析了导引照射激光的脉冲宽度对象限探测器放大组件带宽设计的影响.提出象限探测器放大组件带宽设计方法,以某型激光导引头为例,对该方法的有效性进行了实验验证.结果表明,象限探测器放大组件带宽设计方法可有效...     

基于EFJ模式的宽带高效率Doherty功率放大器设计

将EFJ模式功率放大器应用于Doherty功率放大器的载波功率放大器,利用EFJ类功率放大器的阻抗特性改善了Doherty功率放大器的带宽。此外,还引入后谐波控制网络来提高Doherty功率放大器的效率。功放的输入匹配电路采用阶跃式阻抗匹配来进一步拓展工作带宽。使用CGH40010F GaN 晶体管设计并加工完成了一款宽带高效率Doherty功率放大器。测试结果显示,在3.2~3.7GHz 频段内,饱和输出功率达到43dBm,饱和漏极效率60%~72.5%,增益大于10dB。功率回退6dB时,漏极效率40%~48.5%。     

Design and performance analysis of InP-based high-speed andhigh-sensitivity optoelectronic integrated receivers

A novel transimpedance optoelectronic receiver amplifier suitable for monolithic integration is proposed and analyzed by exploiting state-of-the-art high-speed MSM photodiodes and HBT's based on lattice-matched InGaAs-InAlAs heterostructures on InP substrates. The projected performance characteristics of this amplifier indicate a high transimpedance (≈3.6 kΩ), a large bandwidth (17 GHz), and an excellent optical detection sensitivity (-26.8 dBm) at 17 Gb/s for the standard bit-error-rate of 10^-9. The latter corresponds to an input noise spectral density, √(i_in²/B), of 2.29 pA/√(Hz) for the full bandwidth. The bandwidth of the amplifier can be increased to 30 GHz for a reduced transimpedance (0.82 kΩ) and a lower detection sensitivity, i.e., -21 dBm at 30 Gb/s. The amplifier also achieves a detected optical-to-electrical power gain of 21.5 dBm into a 50 Ω load termination. The design utilizes small emitter-area HBT's for the input cascoded-pair stage, followed by a two-step emitter-follower involving one small and one large emitter-area HBT's. The design strategy of using small emitter-area HBT's is matched by a low-capacitance novel series/parallel connected MSM photodiode. This combined approach has yielded this amplifier's combined high performance characteristics which exceed either achieved or projected performances of any receiver amplifier reported to-date. The paper also discusses the issues concerning IC implementation of the receiver, including the means of realizing a high-value feedback resistor     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable