Ultra-thin oxide reliability: searching for the thickness scaling limit

The degradation and breakdown of ultra-thin oxide layers are discussed. Physical insights are provided for various experimental observations such as stress-induced leakage current, soft breakdown and the polarity gap for Q_BD. The cumulative effect of a wider statistical spread and stronger temperature acceleration for ultra-thin oxides is shown to lead to insufficient reliability below 2.5 nm.     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

High-Performance barium titanate capacitors with double layer structure

High-performance barium titanate (B_aTiO₃) capacitors with excellent electrical and dielectric properties have been made by a two step deposition scheme using reactive rf magnetron sputtering. A novel double layer structure has been developed to reduce the pinholes and improve the electrical properties, such as higher dielectric constant, lower dissipation factor, higher breakdown fields and low leakage currents. Films deposited on a cooled substrate are amorphous whereas those deposited on a heated substrate are poly crystalline. Both polycrystalline and amorphous natures are verified by x-ray diffraction and scanning electron microscopy. Amorphous films have a low leakage current, a high breakdown voltage up to 2.5 x 10⁶ V/cm, and a dielectric constant less than 20. Polycrystalline films yield a high dielectric constant of 330. However, these films also have large leakage currents. The capacitors with the two layer structures,i.e. amorphous layer on top of polycrystal layer, have been shown to be much superior to those prepared by either polycrystal or amorphous layer alone for practical applications. The dielectric constant and breakdown voltage of capacitors with a double layer are found to be as high as 220 and 1.2 x 10⁶ V/cm, respectively. The leakage current is reduced to the same order as the amorphous films alone.     

Off-state breakdown effects on gate leakage current in powerpseudomorphic AlGaAs/InGaAs HEMTs

The effects of off-state breakdown on characteristics of power AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) are investigated in detail. While the gate leakage current is substantially decreased after breakdown stress, no obvious changes in drain-to-source current and transconductance are observed. Prior to breakdown stress, gate leakage current shows a nearly ideal 1/f noise characteristic with an Ig² dependence, suggesting a surface generation-recombination current from the interface of the passivation layer. After stress, the gate current noise can be drastically reduced. The results suggest an alternative for alleviating the gate leakage current in PHEMTs     

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

低漏电、高击穿电容的HDPCVD工艺研究

介绍了一种低漏电、高击穿电容的HDPCVD(ICPCVD)工艺,并对制备的电容进行了电性能分析和失效分析。通过优化确定了工艺的最佳反应条件,研制出的电容其击穿场强达到8.7MV/cm,在电压加到200V时其电容漏电小于0.5μA。通过与传统的PECVD工艺进行对比,充分体现了HDPCVD(ICPCVD)工艺生长介质的低温生长、低漏电、较高击穿场强、无H工艺等优点。随后的失效分析表明,电容上下电极金属对电容成品率有着很大影响。     

浮空层结构的分析

分析了REBULF LDMOS的实验结果，由击穿电压的测试结果验证了模拟仿真中发现的漏电流增加源于n+浮空层的作用，但暴露于表面的n+p结的漏电流使击穿电压降低. 为了解决这个问题，文中分析了具有部分n+浮空层的REBULF LDMOS结构，此结构不但具有降低体内电场的REBULF效应，而且终止于源端体内的n+p结解决了文献［10］中的大漏电流问题. 分析结果表明，击穿电压较一般RESURF LDMOS结构提高60%以上.     

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.     

The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.     

Off-state breakdown and leakage current transport analysis of AlGaN/GaN high electron mobility transistors

Off-state breakdown characteristics of AlGaN/GaN high-electron-mobility transistors have been studied based on drain current injection method. It is found that at low drain current injection level, the observed premature breakdown is caused by excess gate-to-drain leakage current. Nevertheless, at high drain injection current level, buffer-leakage-dominated breakdown proceeds gate-leakage-dominated breakdown as the gate bias increases from pinch-off voltage to deep-depletion voltage. In both breakdown regions, the breakdown voltages show negative temperature coefficients. The buffer-leakage-induced breakdown should be defect-related, which is confirmed by temperature-dependent buffer leakage measurements.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Modelling of gate-induced drain leakage in relation to technological parameters and temperature

The junction breakdown of a MOS transistor with thin gate oxide, imposed undesirable problems. This phenomenon is attributed, particularly, to band-to-band tunnelling occurring in the gate-to-drain overlap region. This is the source of a gate-induced drain leakage (gidl) current I_gidl, limiting therefore the further MOSFET scaling. In this paper we ara interested in the modelling of this current. The model is used to investigate the influence of the technological parameters and the temperature on I_gidl current characteristics.     

Initial leakage current related to extrinsic breakdown in HfO2/Al2O3 nanolaminate ALD dielectrics

Multiple successive breakdown events are reported for HfO₂/Al₂O₃ nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiO_x layer at the silicon substrate/dielectric interface.     

Micro breakdown in small-area ultrathin gate oxides

The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.     

硼硅玻璃掺杂对ZnO压敏电阻器电性能的影响

研究结果表明 ,硼硅玻璃料的掺入超过一定量时会使压敏电场上升。当玻璃料含量占初始配方总质量的 5 %时 ,压敏电场最小 ,非线性系数最小 ,漏电流最大 ;当玻璃料含量占 5 %～ 10 %时 ,随玻璃料掺入量的增加 ,非线性系数明显上升 ,漏电流迅速减小 ,压敏电场迅速上升。     

Analysis of the post-breakdown current in HfO2/TaN/TiN gate stack MOSFETs for low applied biases

A thorough analysis of the post-breakdown current-voltage characteristics in HfO₂high-κ/TaN/TiN gate stacks for low positive applied biases reveals an apparent band gap narrowing of the silicon substrate at the very location of the leakage site. This effect may be caused by the migration of gate material through the percolation path during the breakdown runaway. Additionally, the voltage dependence of the current suggests that the origin of the leakage current is thermal generation within the depletion region close to the breakdown spot. A simple analytical model to deal with this current is proposed.     

Low-leakage, high-efficiency, reliable VPE InGaAs 1.0-1.7 µm photodiodes

High-quality InGaAs vapor-grown photodetectors for the 1.0-1.7 µm spectral region with a 100 µm diameter active area, ∼10-30 nA leakage current, 65-75 V breakdown voltage, 60-80% quantum efficiency, < 0.5 ns pulse rise time, < 1 pW/Hz^1/2noise equivalent power and stable leakage current at 60°C for over 4000 hours are described.