Cross-sectional TEM of Pd/InP and Au/lnP interfaces formed at substrate temperatures near 300 and 77K

Depositing Pd or Au on InP at cryogenic substrate temperatures has previously been found to significantly increase the barrier height of the resulting Schottky diode. In this work, cross-sectional transmission electron microscopy was used to determine the structural differences between metal/semiconductor (MS) interfaces formed at 300K (RT) and at 77K (LT). In the Pd/lnP case, RT samples exhibited a thick amorphous interaction layer at the MS interface, while LT samples only had a thin phosphorous-rich interfacial layer. However, in the Au/InP case, no amorphous interlayers were observed in any of the samples. Instead, a small amount of Au was found to extend into the InP lattice in the RT case which was not present in LT samples. The thermal stability of the barrier height was studied as well. LT Au/lnP samples were found to exhibit a distinct barrier height shift when annealed at 200°C which was linked to a grain coarsening in the polycrystalline Au layer at this temperature. X-ray diffraction was used to verify changes in the polycrystalline metal's average grain size. We conclude that a significant reduction in the interaction between the deposited metal and InP was responsible for the greatly enhanced barrier height observed in LT interfaces.     

台面型InP/InGaAs PIN光伏探测器的p-InP低阻欧姆接触

研究了电子束蒸发淀积的非合金膜系Au/Pt/Ti/p-InP(2×1018cm-3)接触的物理特性,通过450℃、4 min的快速退火,获得了欧姆接触,其比接触电阻为7.3×10-5 Wcm2.接触电极退火后,采用离子溅射法淀积加厚电极Cr/Au.利用俄歇电子能谱(AES)进行深度剖面分析,表明Pt层能够相对有效地阻挡...     

Ag/Ai schottky contacts on n-InP

Schottky contacts have been fabricated onn- InP using a Ag/Al/InP configuration where the Ag and Al thicknesses are 1000 and 40-50Å, respectively. Diodes fabricated on InP substrates withn ≈ 7 x 10¹⁶ cm_-3, have effective barrier heights, Ø_beff, of 0.4 eV and reverse bias leakage current densities of >4 A/cm² atV _r = - 3V. Appropriate heat treating at temperatures between 400–500° C raises barrier heights by as much as 0.25 eV, resulting in Ø_beff ≈ 0.65 eV and reverse bias leakage current densities less than 0.002 A/cm². Diode characteristics are found to vary dramatically with different surface preparations prior to metallization; results of x-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) depth profiling studies indicate that native oxides which are predominantly InPO₄ produce superior contacts and that aluminum first reacts with the native oxide and then migrates through the silver to the free metal surface which results in the dramatic improvements observed upon annealing.     

Au/Zn/Au/p-In P欧姆接触的界面研究

研究了离子束溅射制备的Au/Zn/Au/p-InP欧姆接触的界面特性.在480℃退火15s比接触电阻达到最小,为1.4×1 0-5 Ω·cm 2.利用俄歇电子能谱(AES)和X射线光电子能谱(XPS)研究了接触界面的冶金性质.实验结果表明,在室温下InP中的In就可以扩散到接触的表面,退火后可与Au形成合金.退火后,Zn的扩散可以在p-InP表面形成重掺杂层,从而降低接触势垒高度,减小势垒宽度,有助于欧姆接触的形成;在接触与p-InP的界面产生一个P聚集区,同时Au与InP反应生成Au2P3,其P的2p3/2电子的结合能约为129.2 eV.     

InP mixer diodes with etched via ohmic contacts

InP mixer diodes processed with Ag/TiW/Au Schottky diodes have exhibited a noise figure of 6.5?7.0 dB at 94 GHz. InP surface preparation is shown to be critical in diode performance. An indium-stabilised surface has resulted in a barrier height of 0.45 eV.     

金属/有机高分子膜/n-InP肖特基势垒

本文介绍用有机高分子膜(LB膜和聚酰亚胺)代替n型InP肖特基势垒二极管中的薄氧化层,所得到的肖特基势垒二极管的势垒高度大于0.7eV,反向漏电流小于2.3×10~(-5)A/cm~2,性能稳定.还叙述了有机高分子膜的制备方法,电学测量结果,并与金属/薄氧化膜/n-InP肖特基势垒进行了比较,同时讨论了该法的优缺点.     

Heteroepitaxy of In0.53Ga0.47As on GaAs substrate by low pressure metalorganic chemical vapor deposition for the OEIC applications

InP/In_0.53Ga_0.47As/InP sandwich structure grown by low pressure metalorganic chemical vapor deposition has been investigated, in order to assess the different heteroepitaxy schemes which are based on low temperature (LT) InP metamorphic buffer layer. Photoluminescence (PL) and high resolution X-ray diffraction (HRXRD) and scan probe microscope (SPM) have been carried out to characterize the heteroepitaxy samples. For the best optimum growth condition of 15 nm-thick LT InP buffer at the growth temperature of 450 °C, the full width at half maximum (FWHM) values of the HRXRD, the room-temperature PL were 512 arcsec and 51.7 meV, respectively and the root mean square of SPM is only 0.915 nm.     

退火温度对Au/Ti/4H-SiC肖特基接触特性的影响

采用电子束蒸发法在4H-SiC表面制备了Ti/Au肖特基电极,研究了退火温度对Au/Ti/4H-SiC肖特基接触电学特性的影响.对比分析了不同退火温度下样品的电流密度-电压(J-V)和电容-电压(C-V)特性曲线,实验结果表明退火温度为500℃时Au/Ti/4H-SiC肖特基势垒高度最大,在.J-V测试和C-V测试中分别达到0.933 eV和1.447 eV,且获得理想因子最小值为1.053,反向泄漏电流密度也实现了最小值1.97×10-8 A/cm2,击穿电压达到最大值660 V.对退火温度为500℃的Au/Ti/4H-SiC样品进行J-V变温测试.测试结果表明,随着测试温度的升高,肖特基势垒高度不断升高而理想因子不断减小,说明肖特基接触界面仍然存在缺陷或者横向不均匀性,高温下的测试进一步证明肖特基接触界面还有很大的改善空间.     

Ultraviolet laser-assisted surface treatment of InP with phosphine gas

InP surface has been treated with phosphine (PH₃) gas photodecomposed by ArF excimer laser at a temperature as low as 150° C. It is shown by Auger electron spectroscopy analysis that the photolytic process of PH₃ gas is capable of removing native oxide and depositing simultaneously amorphous P film on the InP surface. Moreover, hydrogenation occurs on and near the surface of InP. An enhancement of the barrier height up to 0.63 eV is demonstrated for MIS Schottky junctions with a thin P layer formed on the treated InP substrates. Furthermore, it is shown that the barrier height varies depending on work function of the Schottky metal on the treated InP. This suggests that the present process causes a reduction in the surface state density which permits weakening of the Fermi level pinning at the surface of InP.     

Cadmium sulfide surface stabilization for InP-based optoelectronic devices

Thin layers of chemical bath deposited cadmium sulfide were used to improve the surface and interface properties of InP and its latticed-matched III-V compounds. X-ray photoelectron spectroscopy indicates chemical reduction of surface oxides and the prevention of subsequent group III or V oxide formation. Photoluminescence spectra, measured between 1.0 and 1.3 μm, indicate a dramatic reduction in phosphorus vacancies following CdS treatment. Metalinsulator-semiconductor capacitors fabricated onn-type InP substrates with CdS interlayers display near-ideal quasi-static response and interface-state densities in the low 10¹¹/eVcm² range. Thin CdS layers were used to passivate the surface of InAlAs/InGaAs high electron mobility transistors (HEMTs) and metal-semiconductor-metal (MSM)photodetectors.AfterCdS treatment, Schottky diode barrier heights of 0.6 eV were regularly obtained. For HEMTs, drain-togate current ratios of 8 × 10⁴ were observed after CdS treatment. For a new backside illuminated MSM design, the dark current of CdS-treated samples was reduced three orders of magnitude to below 1 nA.     

Effect of deposition temperature on electric conduction and microstructure of Au films

Electric conduction was studied on thin gold films deposited at room (RT = 300 K) and liquid nitrogen temperature (LT = 77 K). Microstructure properties, and surface morphology of metal films were investigated by transmission electron spectroscopy (TEM) and atomic force microscope (AFM). The film thickness was chosen less than several hundred angstroms. Electrical measurement found that the LT film showed several orders lower resistance compared to the film obtained at room temperature at very low (about 100 Å) thickness. TEM study found that the LT films showed much smaller density of grain boundaries than that of the RT samples. In AFM observation, for film thickness of 100 Å, LT film showed smoother and continuous surface while the RT film consisted of discrete islands. When the thickness increased to be 200 Å, the LT film showed much larger-sized grains compared to that of the RT film. It is possible that for LT deposition, two-dimensional larger-sized grains were first formed at low temperature deposition which later extended to be three-dimensional.     

Electrical characteristics of high performance Au/n-GaN schottky diodes

Au/n-GaN Schottky diodes with the Au electrode deposited at low temperature (LT=77K) have been studied. In comparison, the same chip of GaN epitaxial layer was also used for room temperature Schottky diodes. The low temperature Schottky diodes exhibit excellent performance. Leakage current density as low as 2.55×10⁻¹¹ A·cm⁻² at −2.5 V was obtained in the LT Schottky diodes. The linear region in the current-voltage curve at forward bias extends more than eight orders in current magnitude. Current-voltage-temperature measurements were carried out to study the characteristics of the LT Schottky diodes. A typical barrier height of about 1.32 eV for the LT diode, which is the highest value ever reported, was obtained. The obvious enhancement in electrical performance makes the LT processing a very promising technique for GaN device application although the detailed mechanisms for the LT Au/n-GaN Schottky diodes are still under investigation.     

Schottky barrier heights of n-type and p-type Al0.48In0.52As

The authors report electrical measurements on four different metal contacts which formed Schottky barriers to lightly doped complementary n- and p-type Al_0.48In_0.52As epitaxial material grown by molecular beam epitaxy on semi-insulating InP substrates. The Schottky contact metals studied were Au, Al, Pt, and tri-layer Ti/Pt/Au. The Schottky barrier heights varied from 0.560 eV for Al on n-type AlInAs to 0.905 eV for Al on p-type AlInAs, with intermediate values for the other metals studied. The sum of n- and p-type Schottky barrier heights for each metal contact ranged from 1.440 to 1.465 eV, in good agreement with the accepted Al_0.48In_0.52As bandgap value of 1.45 eV     

p-InP/TiPdAu体系的冶金行为和电学特性

正 (一)引言 近年来InP在光电和微波器件中的应用已引起广泛重视。对InP的欧姆接触和肖特基势垒已有报道,这些结果表明,Bp较Bn大,n-InP的比接触电阻较p-lnP的低。以InP为衬底的多层结构器件中,表面层有时是p-InP,因此研究p-InP与接触金属界面上的冶金行为和电学特性,对改善器件参数和提高器件的可靠性有实际意义。对p-InP与接触金属Pd,Mg/Ag,Au-Zn,Mg/Au,Pd/Ag的界面特性,已有用俄歇电子能谱(AES)和电子探针(EP)进行的研究结果     

Novel metal-semiconductor-metal photodetectors on bulk semi-insulating indium phosphide

Depositing Pd or An on InP at substrate temperatures near 77 K (LT) has previously been found to significantly reduce the interaction between the metal and semiconductor upon formation of the interface. In this letter, this technique was used to fabricate metal-semiconductor-metal photodetectors (MSMPDs) on semi-insulating (SI) InP substrates with superior characteristics compared to detectors formed using standard room temperature (RT) metal deposition. Detectors having a LT-Ps-SI-InP structure had a dark current of 80 nA at 5 V, which was a factor of 4 lower than the dark current of conventional MSMPDs. Additionally, LT-Pd-SI-InP MSMPDs exhibited excellent saturation characteristics and a responsivity of 0.75 A/W. Detectors with an indium-tin-oxide (ITO)-LT-Au (200 /spl Aring/)-SI-InP structure had a higher responsivity of 1.0 A/W, due to the relative transparency of this metallization. In contrast, MSMPDs with RT metallizations had poor saturation characteristics, consistent with the results of others. The difference in the illuminated characteristics of MSMPDs with RT and LT metallizations was due to a change in the internal photoconductive gain mechanism. In RT detectors, hole trapping at interface states near the cathode dominated the gain mechanism. In LT detectors, the difference in carrier transit-times dominated.     

High performance Schottky contacts on Se-doped AlxGa1−xAs by cryogenic processing

Al_xGa_1−xAs samples were grown on Se-doped Al_xGa_1−xAs layer above GaAs substrate by metalorganic chemical vapor deposition (MOCVD). It was reported that the crystal quality of the re-growth Al_xGa_1−xAs layer can be improved significantly when an Se-doped Al_xGa_{1 − x}As layer was used. The surface carrier concentration, however, was increased as a result of the Se-doping. Therefore, it could be difficult to obtain a high performance Schottky contacts on such a structure for practical devices application. In this work, Schottky contacts to Al_xGa_1−xAs/Se-doped Al_xGa_1−xAs were formed by cryogenic processing. In such a processing, the Schottky metal deposition was carried out with the sample cooled to a low temperature (LT) of 77 K. The Schottky barrier height was increased significantly in a Au/Al_xGa_1−xAs/Se-doped Al_xGa_1−xAs contact. The leakage current, for the LT contact, was nearly 4 orders lower than that of contact made at room temperature. A current transport mechanism dominated by thermionic emission for the LT contacts was found from current-voltage-temperature (I-V-T) measurement.     

Pt／Si界面反应与肖特基势垒形成的研究

利用俄歇电子能谱，二次离子质谱，深能级瞬态谱（ＤＬＴＳ）和Ｃ－Ｖ法等测量方法，详细研究了Ｐｔ／Ｓｉ和Ｐｔ硅化物／Ｓｉ界面的反应性质，原子结构及杂质／缺陷的分布，讨论了它们对肖特基势垒的形成，势垒特发生和势垒高度的影响。     

Annealing and Measurement Temperature Dependence of W<Subscript>2</Subscript>B- and W<Subscript>2</Subscript>B<Subscript>5</Subscript>-Based Rectifying Contacts to <Emphasis Type="Italic">p</Emphasis>-GaN

Schottky contact formation on p-GaN using W₂B/Pt/Au and W₂B₅/Pt/Au metallization schemes was investigated using x-ray photoelectron spectroscopy (XPS), current-voltage (I-V), and Auger electron spectroscopy measurements. The Schottky barrier height (SBH) determined from XPS is 2.71 eV and 2.87 eV for as-deposited W₂B- and W₂B₅-based contacts, respectively. By comparison, fitting of the I-V curves using the thermionic field emission model gives unphysical SBHs > 4 eV due to the presence of an interfacial layer acting as an additional barrier to carrier transport. Upon annealing to ∼600–700°C, the diodes show slight deterioration in rectifying behavior due to the onset of metallurgical reactions with the GaN. The experimental dependence of the reverse leakage current on bias and measurement temperature is inconsistent with both thermionic emission and thermionic field emission models, suggesting that leakage must originate from other mechanisms such as surface leakage or generation in the depletion layer through deep-level defects.     

Effect of semiconductor growth method and bulk doping on fermi level stabilization for aluminum and gold contacts on n- and p-GaAs(100)

Effects of substrate doping and growth method on interface deep level formation and Schottky barrier height were investigated using low-energy catho doluminescence and soft x-ray photoemission spectroscopy. Our results reveal that for Au/GaAs(100) contacts Fermi level (E_F) stabilization energy shows little sensitivity to either substrate growth technique or the type of doping, and Iles in the 0.37 to 0.47 eV range above the valence band maximum (E_v). In contrast, the E_F position at Al/GaAs(100) interfaces is highly sensitive to substrate growth method for n-type GaAs, but shows no significant difference between the epitaxial and melt-grown p-type GaAs. Furthermore, for a specific substrate dopant type and growth method, gold and aluminum produce barrier heights which differ by 0.05 to 0.50 eV, depending upon the substrate growth and dopant properties. Cathodoluminescence results demonstrate that discrete surface and interface states responsible for E_F stabilization at these metal/GaAs junctions are highly sensitive to the substrate growth technique, as well as to the specific metal contact. This work emphasizes that both substrate crystalline and electronic properties, as well as the adatom-specific interface chemistry are crucial for the electrostatic barrier height formation at metal/GaAs contacts.     

Electrical Properties and Current Transport Mechanisms of the Au/n-GaN Schottky Structure with Solution- Processed High-k BaTiO3 Interlayer

The electrical properties and current transport mechanisms of Au/BaTiO₃ (BTO)/n-GaN metal–insulator–semiconductor (MIS) structures have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements at room temperature. Experimental results reveal that the MIS structure has a higher rectification ratio with low reverse leakage current compared with the Au/n-GaN metal–semiconductor (MS) structure. The calculated barrier height of the Au/BTO/n-GaN MIS structure [0.87 eV (I–V)/1.02 eV (C–V)] increases compared with the Au/n-GaN MS structure [0.73 eV (I–V)/0.96 eV (C–V)]. The series resistance is extracted using Cheung’s functions, and the values are in good agreement with each other. Furthermore, the energy distribution of the interface state density is estimated from the forward-bias I–V data. It is noteworthy that the interface state density of the MIS structure is lower than that of the MS structure. In both MS and MIS structures under forward-bias conditions, ohmic and space-charge-limited conduction mechanisms are identified at lower and higher voltages, respectively. Investigations reveal that Poole–Frenkel emission dominates the reverse leakage current in both Au/n-GaN and Au/BTO/n-GaN structures.