Demultiplexers for Nanoelectronics Constructed From Nonlinear Tunneling Resistors

When using linear resistors to implement nanoelectronic resistor-logic demultiplexers, codes can be used to improve the voltage margins of these circuits. However, the resistors which have been fabricated in nanoscale crossbars are observed to be nonlinear in their current versus voltage (I-V) characteristics, showing an exponential dependence of current on voltage; we call these devices tunneling resistors. The introduction of nonlinearity can either improve or degrade the voltage margin of a demultiplexer circuit, depending on the particular code used. Therefore, the criterion for choosing codes must be redefined for demultiplexer circuits built from this type of nonlinear resistor. We show that for well-chosen codes, the nonlinearity of the resistors can be advantageous, producing a better voltage margin than can be achieved with linear resistors     

Effect of Conductance Variability on Resistor-Logic Demultiplexers for Nanoelectronics

On a mixed-scale nanoelectronic crossbar, in which nanowires cross CMOS-scale wires at right angles, a demultiplexer circuit may be laid out using configurable resistors at the crosspoint junctions. This circuit can function as an interface between conventional CMOS microelectronic circuitry and the smaller nanocircuitry by allowing a few CMOS address lines to control a much larger number of nanowires. The voltage margin properties of these resistor-demultiplexers can be improved by basing them on error-correcting codes. In any real fabrication process, the conductances of the resistors in the demultiplexer circuit will be distributed over a range of values. Using simulation, we investigate how variability in the conductances affects the voltages on the output lines of the demultiplexer, and the related voltage margin of the overall circuit. The simulation results provide a simple quantitative relationship revealing that the voltage variability is smaller than the component variability.     

Defect-tolerant architectures for nanoelectronic crossbar memories

We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of defective memory cell fraction. While our calculations are based on a particular ("CMOL") memory topology, with naturally segmented nanowires and an area-distributed nano/CMOS interface, for realistic parameters our results are also applicable to "global" crossbar memories with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development) may overcome purely semiconductor memories in useful bit density if the fraction of nanodevice defects (stuck-on-faults) is below approximately 15%, even under rather tough, 30 ns upper bound on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crossbar memories may be far superior to the densest semiconductor memories by providing, e.g., a 1 Tbit/cm2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better than those reported in literature earlier, including our own early work, mostly due to more advanced error correcting codes.     

Experimental demonstration of a defect-tolerant nanocrossbar demultiplexer

Ultradense memory and logic circuits fabricated at local densities exceeding 100 × 10(9) cross-points per cm(2) have recently been demonstrated with nanowire crossbar arrays. Practical implementation of such nanocrossbar circuitry, however, requires effective demultiplexing to solve the problem of electrically addressing individual nanowires within an array. Importantly, such a demultiplexer (demux) must also be tolerant of the potentially high defect rates inherent to nanoscale circuit fabrication. We have built a 50?nm half-pitch nanocrossbar circuit using imprint lithography and configured it for a demux application. Utilizing a class of Hamming codes in the hardware design, we experimentally demonstrate defect-tolerant demux operations on a 12 × 8 nanocrossbar array with up to two stuck-open defects per addressed line.     

Low-density parity-check codes for volume holographic memory systems

We investigate the application of low-density parity-check (LDPC) codes in volume holographic memory (VHM) systems. We show that a carefully designed irregular LDPC code has a very good performance in VHM systems. We optimize high-rate LDPC codes for the nonuniform error pattern in holographic memories to reduce the bit error rate extensively. The prior knowledge of noise distribution is used for designing as well as decoding the LDPC codes. We show that these codes have a superior performance to that of Reed-Solomon (RS) codes and regular LDPC counterparts. Our simulation shows that we can increase the maximum storage capacity of holographic memories by more than 50 percent if we use irregular LDPC codes with soft-decision decoding instead of conventionally employed RS codes with hard-decision decoding. The performance of these LDPC codes is close to the information theoretic capacity.     

Irregular repeat-accumulate codes for volume holographic memory systems

We investigate the application of irregular repeat-accumulate (IRA) codes in volume holographic memory (VHM) systems. We introduce methodologies to design efficient IRA codes. We show that a judiciously designed IRA code for a typical VHM can be as good as the optimized irregular low-density-parity-check codes while having the additional advantage of lower encoding complexity. Moreover, we present a method to reduce the error-floor effect of the IRA codes in the VHM systems. This method explores the structure of the noise pattern in holographic memories. Finally, we explain why IRA codes are good candidates for the VHM systems.     

A Novel Reference Scheme for Reading Passive Resistive Crossbar Memories

A great effort today is concentrated on the development of resistive hysteretic materials and their related memory architecture. Resistive memories have a promising future to replace all current memory technologies to present an all-in-one memory solution. Passive resistive memories are of a special importance, since they can be scaled into the nanometer range without losing their functionality. This work is concerned with a novel scheme for generating reference voltages for the read operation. The scheme can be used with any passive crossbar based memory, regardless of the materials used for the implementation of the memory elements     

Defect tolerance in resistor-logic demultiplexers for nanoelectronics

Since defect rates are expected to be high in nanocircuitry, we analyse the performance of resistor-based demultiplexers in the presence of defects. The defects observed to occur in fabricated nanoscale crossbars are stuck-open, stuck-closed, stuck-short, broken-wire, and adjacent-wire-short defects. We analyse the distribution of voltages on the nanowire output lines of a resistor-logic demultiplexer, based on an arbitrary constant-weight code, when defects occur. These analyses show that resistor-logic demultiplexers can tolerate small numbers of stuck-closed, stuck-open, and broken-wire defects on individual nanowires, at the cost of some degradation in the circuit's worst-case voltage margin. For stuck-short and adjacent-wire-short defects, and for nanowires with too many defects of the other types, the demultiplexer can still achieve error-free performance, but with a smaller set of output lines. This design thus has two layers of defect tolerance: the coding layer improves the yield of usable output lines, and an avoidance layer guarantees that error-free performance is achieved.     

Applications of bubble devices

The applications of magnetic bubbles that are currently seen as most attractive and the current status of development of such devices are considered. A major application is thought to occur in solid-state mass memories. An attractive form of organization is possible whereby relatively short access times can be achieved while using only a small number of read and write circuits. A repertory dialer memory, which has been chosen as a test vehicle, has been developed. The design and performance of the propagating circuits, the self-latching magnetic gates and the generator, which comprise the memory, are discussed. A novel area of application may be in pulse code modulation (PCM) switching networks. It is shown how a network operating as a PCM crossbar switch can be designed using bubbles. A circuit is described which can eliminate the delay associated with bubble propagation in such networks.     

Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays

Recently a prototype of complementary resistive switches has been proposed to solve the sneak-path problem in passive crossbar memory arrays. To further evaluate the potential of this novel cell structure for practical applications, we present a modeling analysis to capture its switching dynamics and analyze its unique read/write schemes. The model is corroborated by experimental data. We found a trade-off between the read voltage window and write voltage window. The constraint from avoiding disturbance on unselected cells is critical for proper functionality, which in turn limits the writing speed.     

Observation of Resistive Switching Behavior in Crossbar Core–Shell Ni/NiO Nanowires Memristor

The crossbar structure of resistive random access memory (RRAM) is the most promising technology for the development of ultrahigh‐density devices for future nonvolatile memory. However, only a few studies have focused on the switching phenomenon of crossbar RRAM in detail. The main purpose of this study is to understand the formation and disruption of the conductive filament occurring at the crossbar center by real‐time transmission electron microscope observation. Core–shell Ni/NiO nanowires are utilized to form a cross‐structure, which restrict the position of the conductive filament to the crosscenter. A significant morphological change can be observed near the crossbar center, which results from the out‐diffusion and backfill of oxygen ions. Energy dispersive spectroscopy and electron energy loss spectroscopy demonstrate that the movement of the oxygen ions leads to the evolution of the conductive filament, followed by redox reactions. Moreover, the distinct reliability of the crossbar device is measured via ex situ experiments. In this work, the switching mechanism of the crossbar core–shell nanowire structure is beneficial to overcome the problem of nanoscale minimization. The experimental method shows high potential to fabricate high‐density RRAM devices, which can be applied to 3D stacked package technology and neuromorphic computing systems.     

Nanoelectronics from the bottom up

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.     

Experimental demonstration of gray-scale sparse modulation codes in volume holographic storage

We discuss experimental results of a versatile nonbinary modulation and channel code appropriatefor two-dimentional page-oriented holographic memories. An enumerative permutation code is used to provide a modulation code that permits a simple maximum-likelihood detection scheme. Experimental results from the IBM Demon testbed are used to characterize the performance and feasibility of the proposed modulation and channel codes. A reverse coding technique is introduced to combat the effects of error propagation on the modulation-code performance. We find experimentally that level-3 pixels achieve the beet practical result, offering an 11-35% improvement in capacity and a 12% increase in readout rate as compared with local binary thresholding techniques.     

Principles of constructing failure-resistant measurement technology microprocessor devices witha posteriori correction of multiple errors (discussion)

A method is considered for ensuring failure-resistant operation of computer memory devices which is based on linear correcting codes with a posteriori correction of multiple errors. The proposed method makes it possible to extend the correcting possibilities of the code, i.e., to determine the configuration of any error with minimum code redundancy, requirements of hardware and time. Translated from Izmeritel'naya Tekhnika, No. 4, pp. 21–28, April. 2000.     

Methods for Correcting Multiple Errors of Information Storage Devices Used in Microprocessor Facilities of Measurement Technology (a discussion)

A method is considered for ensuring resistance to failure in operational computer memory devices by utilizing linear correcting codes with a posteriori correction of multiple errors. The proposed method makes it possible to extend the correcting possibilities of the code, i.e., to determine the configuration of any error with the minimum code redundancy and the lowest hardware and software costs.     

High‐Performance Solution‐Processed Organo‐Metal Halide Perovskite Unipolar Resistive Memory Devices in a Cross‐Bar Array Structure

Resistive random access memories can potentially open a niche area in memory technology applications by combining the advantages of the long endurance of dynamic random‐access memory and the long retention time of flash memories. Recently, resistive memory devices based on organo‐metal halide perovskite materials have demonstrated outstanding memory properties, such as a low‐voltage operation and a high ON/OFF ratio; such properties are essential requirements for low power consumption in developing practical memory devices. In this study, a nonhalide lead source is employed to deposit perovskite films via a simple single‐step spin‐coating method for fabricating unipolar resistive memory devices in a cross‐bar array architecture. These unipolar perovskite memory devices achieve a high ON/OFF ratio up to 10⁸ with a relatively low operation voltage, a large endurance, and long retention times. The high‐yield device fabrication based on the solution‐process demonstrated here will be a step toward achieving low‐cost and high‐density practical perovskite memory devices.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

Robust Intermediate Read-Out for Deep Submicron Technology CMOS Image Sensors

In this paper, a CMOS image sensor featuring a novel spiking pixel design and a robust digital intermediate read-out is proposed for deep submicron CMOS technologies. The proposed read-out scheme exhibits a relative insensitivity to the ongoing aggressive scaling of the supply voltage. It is based on a novel compact spiking pixel circuit, which combines digitizing and memory functions. Illumination is encoded into a Gray code using a very simple yet robust Gray 8-bit counter memory. Circuit simulations and experiments demonstrate the successful operation of a 64 64 image sensor, implemented in a 0.35 CMOS technology. A scalability analysis is presented. It suggests that deep sub-0.18 will enable the full potential of the proposed Gray encoding spiking pixel. Potential applications include multiresolution imaging and motion detection.     

Optical smart-pixel-based Clos crossbar switch

We present the design of an optically interconnected Clos crossbar switch that uses three smart-pixel devices. This optical Clos architecture is also well matched to a space-wavelength switch that arbitrarily permutes data streams between wavelength-division multiplexed channels on an array of fibers. We have designed a hybrid complementary metal-oxide semiconductor-self-electro-optic device (CMOS-SEED) crossbar smart-pixel array for use in a 16-channel optical Clos switch. The crossbar devices also have an 8 x 8 array of multiple-quantum-well diodes that can be configured electrically as modulators with eight bit planes of randomly addressable local memory or as receivers with adjustable gain and threshold. We show that the current hybrid-SEED technology should support a 1024-channel Clos switch operating at 500 Mbits/s per channel if pixel power consumption can be reduced.