Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells.     

Simulation of a Ge-Si hetero-nanocrystal memory

The Ge/Si hetero-nanocrystal as a floating gate has been discussed and improved. The charge stored in the quantum well formed by SiO/sub 2/-Ge-Si has to be thermally activated to the valence band of the Si nanocrystal before it can leak to the substrate which significantly reduces the leakage current from the charge storage node (nanocrystal) to the substrate. The simulation shows that the flash memory with Ge-Si (3 nm/3 nm) hetero-nanocrystal floating gates possesses a retention time of about ten years with a tunneling oxide of only 2 nm. Both writing and erasing speeds are fast in the Ge-Si hetero-nanocrystal memories, which is similar to that in the memory based on Si nanocrystals only.     

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co(3)O(4)) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented.     

Temperature-dependent memory characteristics of silicon-oxide-nitride-oxide-silicon thin-film-transistors

This study investigates the temperature-dependent memory characteristics of polycrystalline silicon thin-film transistors with oxide/nitride/oxide stack gate dielectrics and N⁺ poly-Si gate structures for nonvolatile memory application. As the device was programmed by Fowler-Nordheim tunneling at high temperature, some electrons captured in shallow traps could obtain enough thermal energy to de-trap to the gate, resulting in low programming efficiency. As the programming time increases, the hole injection through the blocking oxide from the gate would further lead the threshold voltage to decrease. In addition, the retention characteristic of the device programmed at higher temperature exhibits better charge storage ability. Because the electrons trapped in the shallow traps of the nitride layer can be easily de-trapped when temperature rises, the memory characteristics are mainly dominated by charges stored in the deep traps.     

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al(2)O(3) gate oxides

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8?V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.     

Flexible Nonvolatile Transistor Memory with Solution‐Processed Transition Metal Dichalcogenides

Nonvolatile field‐effect transistor (FET) memories containing transition metal dichalcogenide (TMD) nanosheets have been recently developed with great interest by utilizing some of the intriguing photoelectronic properties of TMDs. The TMD nanosheets are, however, employed as semiconducting channels in most of the memories, and only a few works address their function as floating gates. Here, a floating‐gate organic‐FET memory with an all‐in‐one floating‐gate/tunneling layer of the solution‐processed TMD nanosheets is demonstrated. Molybdenum disulfide (MoS₂) is efficiently liquid‐exfoliated by amine‐terminated polystyrene with a controlled amount of MoS₂ nanosheets in an all‐in‐one floating‐gate/tunneling layer, allowing for systematic investigation of concentration‐dependent charge‐trapping and detrapping properties of MoS₂ nanosheets. At an optimized condition, the nonvolatile memory exhibits memory performances with an ON/OFF ratio greater than 10⁴, a program/erase endurance cycle over 400 times, and data retention longer than 7 × 10³ s. All‐in‐one floating‐gate/tunneling layers containing molybdenum diselenide and tungsten disulfide are also developed. Furthermore, a mechanically‐flexible TMD memory on a plastic substrate shows a performance comparable with that on a hard substrate, and the memory properties are rarely altered after outer‐bending events over 500 times at the bending radius of 4.0 mm.     

Peculiar aspects of nanocrystal memory cells: data and extrapolations

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.     

Hybrid Flexible Resistive Random Access Memory‐Gated Transistor for Novel Nonvolatile Data Storage

Here, a single‐device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three‐layered structure is fabricated by utilizing solution‐processed MoS₂ nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene‐based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well‐defined memory window. Compared to the reference flash memory device based on the MoS₂ floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM‐gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well‐defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high‐performance flexible electronics.     

Nonvolatile floating gate memory containing AgInSbTe-SiO2 nanocomposite layer and capping the HfO2/SiO2 composite blocking oxide layer

An extremely large memory window shift of about 30.7 V and high charge storage density =2.3 × 10(13) cm(-2) at ± 23 V gate voltage sweep were achieved in the nonvolatile floating gate memory (NFGM) device containing the AgInSbTe (AIST)-SiO(2) nanocomposite as the charge trap layer and HfO(2)/SiO(2) as the blocking oxide layer. Due to the deep trap sites formed by high-density AIST nanocrystals (NCs) in the nanocomposite matrix and the high-barrier-height feature of the composite blocking oxide layer, a good retention property of the device with a charge loss of about 16.1% at ± 15 V gate voltage stress for 10(4) s at the test temperature of 85?°C was observed. In addition to inhibiting the Hf diffusion into the programming layer, incorporation of the SiO(2) layer prepared by plasma-enhanced chemical vapor deposition in the sample provided a good Coulomb blockade effect and allowed significant charge storage in AIST NCs. Analytical results demonstrated the feasibility of an AIST-SiO(2) nanocomposite layer in memory device fabrication with a simplified processing method and post-annealing at a comparatively low temperature of 400?°C in comparison with previous NC-based NFGM studies.     

浮栅存储器的单粒子辐射效应研究进展

综述了浮栅存储器的单粒子效应国外研究进展,对浮栅存储器控制电路及存储单元的单粒子效应进行详细分析和讨论。指出控制电路是浮栅存储器单粒子效应的关键部件以及重离子轰击使浮栅存储器数据保持特性退化;阐述了浮栅存储单元辐射后可能的电荷损失机制。最后指出纳米晶浮栅存储器具有好的抗辐射能力。     

First dc Measurements of Electrons on Liquid Helium: the Helium-FET

We present the first dc-measurements on a 2-dimensional (2D) electron system floating above a liquid ⁴ He-film which covers a structured metal surface. With our arrangement of a source-, gate-, and drain-electrode a 2-dimensional charge transport is realized in analogy to a field-effect-transistor. The electrons which are moving along the x-direction due to different dc potentials are directly measured. This dc current, of the order of pA, is strongly dependent on the applied split-gate voltage. So the electrons were laterally confined to a narrow channel between the two gate electrodes. The effective width of the channel is reduced by the gate potential, so that a quasi-1D configuration can be realized. The measured electron current through the split-gate is analyzed and discussed on grounds of reduced dimensionality and 1D electron transport behaviour.     

Reduce cell to cell charge interference by virtual ground inclusion in 3-dimensional vertical gate NAND flash memory

In this work, we propose a structural modification to the 3-dimensional vertical gate NAND flash memory that will reduce the charge interference caused by stored charge on the opposite facing cell. In the barrier oxide structure (BOS), an oxide layer was inserted into the center of the body to physically block the conduction electrons moving to and from the channel regions influenced by the charge stored on either of the Oxide-Nitride-Oxide (ONO) trap layers. In the virtual ground structure (VGS), a highly p-type doped poly silicon layer was inserted to act as a virtual ground to reduce the electric-field changes caused by the stored change on the ONO trap layers. We investigated the I-V characteristics of the different structures using 3-D TCAD simulation tool, depending on the body type (crystalline or poly silicon) at double programming and single programming. We confirmed that the charge interference problem was reduced significantly by the BOS and VGS modifications in the crystalline silicon and high quality poly silicon body structures.     

A Tunneling Dielectric Layer Free Floating Gate Nonvolatile Memory Employing Type‐I Core–Shell Quantum Dots as Discrete Charge‐Trapping/Tunneling Centers

A nonvolatile memory with a floating gate structure is fabricated using ZnSe@ZnS core–shell quantum dots as discrete charge‐trapping/tunneling centers. Systematical investigation reveals that the spontaneous recovery of the trapped charges in the ZnSe core can be effectively avoided by the type‐I energy band structure of the quantum dots. The surface oleic acid ligand surrounding the quantum dots can also play a role of energy barrier to prevent unintentional charge recovery. The device based on the quantum dots demonstrates a large memory window, stable retention, and good endurance. What is more, integrating charge‐trapping and tunneling components into one quantum dot, which is solution synthesizable and processible, can largely simplify the processing of the floating gate nonvolatile memory. This research reveals the promising application potential of type‐I core–shell nanoparticles as the discrete charge‐trapping/tunneling centers in nonvolatile memory in terms of performance, cost, and flexibility.     

Nonvolatile Analog Memory Transistor Based on Carbon Nanotubes and C60 Molecules

A nonvolatile analog memory transistor is demonstrated by integrating C60 molecules as charge storage molecules in the transistor gate, and carbon nanotubes (CNTs) in the transistor channel. The currents through the CNT channel can be tuned quantitatively and reversibly to analog values by controlling the number of electrons trapped in the C60 molecules. After tuning, the electrons trapped in the C60 molecules in the gate, and the current through the CNT channel, can be preserved in a nonvolatile manner, indicating the characteristics of the nonvolatile analog memory.     

Capacitorless 1T-DRAM on crystallized poly-Si TFT

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.     

Fabrication and characterization of twin poly-Si thin film transistors EEPROM with a nitride charge trapping layer

This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 10(4) P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.     

Operation of nanocrystalline-silicon-based few-electron memory devices in the light of electron storage, ejection, and lifetime characteristics

A metal-oxide-semiconductor field-effect transistor memory device using nanocrystalline Si (nc-Si) dots as a floating gate over a short and narrow channel has been fabricated. Its operation at 77 K presents experimental evidence of storing and ejection of electrons associated with the nc-Si dot in the active area of the device. Though the lifetime of a single electron is apparently longer than the case when it is associated with another electron in the same nc-Si dot, a distribution in lifetime has been generally observed for the stored electrons in the nc-Si dots with the present memory devices.     

Retention characteristics of Schottky barrier tunneling transistor-nano floating gate memory with various side walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.     

Symmetric Ultrafast Writing and Erasing Speeds in Quasi‐Nonvolatile Memory via van der Waals Heterostructures

Due to the large gap in timescale between volatile memory and nonvolatile memory technologies, quasi‐nonvolatile memory based on 2D materials has become a viable technology for filling the gap. By exploiting the elaborate energy band structure of 2D materials, a quasi‐nonvolatile memory with symmetric ultrafast write‐1 and erase‐0 speeds and long refresh time is reported. Featuring the 2D semifloating gate architecture, an extrinsic p–n junction is used to charge or discharge the floating gate. Owing to the direct injection or recombination of charges from the floating gate electrode, the erasing speed is greatly enhanced to nanosecond timescale. Combined with the ultrafast write‐1 speed, symmetric ultrafast operations on the nanosecond timescale are achieved, which are ≈10⁶ times faster than other memories based on 2D materials. In addition, the refresh time after a write‐1 operation is 219 times longer than that of dynamic random access memory. This performance suggests that quasi‐nonvolatile memory has great potential to decrease power consumption originating from frequent refresh operations, and usher in the next generation of high‐speed and low‐power memory technology.     

Silicon nanocrystals synthesized by electron-beam co-evaporation method and their application for nonvolatile memory

In this paper, the silicon nanocrystals (Si NCs)/SiO₂ hybrid films designed for nonvolatile memory applications are prepared by electron-beam co-evaporation of Si and SiO₂. Transmission electron microscopy images and Raman spectra verify the formation of Si NCs. Metal-oxide-semiconductor capacitor structure with Si NCs embedded in the gate oxide is fabricated to characterize the memory behaviors. High-frequency capacitance-voltage and capacitance-time measurements further demonstrate the memory effect of the structure resulting from the charging or discharging behaviors of Si NCs. It is found that the memory window can be changed by adjusting the Si/SiO₂ wt. ratio in source material. The memory devices with Si NCs/SiO₂ hybrid film as floating gate yield good retention characteristics with small charge loss.