低能氦离子注入引入的量子阱混杂带隙波长蓝移

提出了采用低能氦离子注入多量子阱(MQW)材料和合适的快速退火条件,实现了MQW带隙波长的蓝移.用这种材料制作了FP腔激光器,与未注入器件相比,实现了37nm的激射波长蓝移.     

低能氦离子注入引入的量子阱混杂带隙波长蓝移

提出了采用低能氦离子注入多量子阱(MQW)材料和合适的快速退火条件,实现了MQW带隙波长的蓝移.用这种材料制作了FP腔激光器,与未注入器件相比,实现了37nm的激射波长蓝移.     

Cu溅射诱导增强量子阱混杂实验研究

在InP基异质结InGaAsP多量子阱(MQW)结构上溅射Cu/SiO2复合层,开展了量子阱混杂(QWI)材料的实验研究。经快速退火(RTA),实现了比常规无杂质空位扩散(IFVD)方法更大的带隙波长蓝移量。在750℃、200s的退火条件下,获得最大172nm的波长蓝移;通过改变退火条件,可实现不同程度的蓝移,满足光子集成技术中不同器件对带隙波长的需求。为了验证其用于光子集成领域的可行性,利用混杂技术分别制备了宽条激光器和单片集成电吸收调制激光器(EML)。在675℃退火温度,80s、120s和200s的退火时间下分别实现了61、81和98nm的波长蓝移;并且,相应的宽条激光器的电激射光(EL)谱偏调量与其材料的光致荧光(PL)谱偏调量基本一致。在675℃、120s退火条件下,制备的EML集成器件中,电吸收调制器(EAM)和分布反馈(DFB)激光器区的蓝移量分别83nm和23.7nm,相对带隙差为59.3nm。EML集成器件在激光器注入电流为100mA、调制器零偏压时出光功率达到9.6mW;EAM施加-5V反向偏压时静态消光比达16.4dB。     

GaAs／AlGaAs量子阱红外探测器的光荧光表征

对GaAs/AlGaAs量子阱红外探测器器件进行显微荧光光谱（μ－PL）测量,光谱中表征势垒、势阱基态间光跃迁能量位置的荧光峰值接与势垒中Al含量相关,通过光谱实验上对势垒和量子阱带间跃迁能量的确定并结合有效质量理论的计算,获得了Al组分和阱宽值,并由此推算出相应的红外探测响应波长,与光电流谱的结果相比吻合良好,这种材料的测量结果有利于器件制备的材料筛选。     

InGaAsP量子阱混合技术理论及模拟研究

本文以品格中原子的扩散理论为基础，分析了四元系InGaAsP半导体材料中Ⅲ、Ⅴ族原子的扩散规律，建立了量子阱和超晶格结构中量子阱混合(QWI)的理论模型，模拟计算了半导体材料中组分浓度与扩散长度的关系，以及应变与扩散长度的关系，计算分析了应变对量子阱带隙、带结构和量子跃迁的影响，获得了一些有价值的结论，为量子阱混合试验和量子阱及超晶格集成器件的开发和研究提供了重要的理论基础。     

InGaAs(P)/InP光电子集成(OEIC)器件的研究与进展

单片集成光电子器件是采用光电子集成(OEIC)技术,将集成光路与集成电路融合为一体的一种器件,以完成发射、接收等特定的电路功能.本文着重于1.0～1.6μm波长范围的单片集成先电子器件,简要介绍目前正在广泛研究的OEIC的结构类型及其性能水平,讨论有关的材料生长技术和某些关键的工艺技术问题.     

基于空间控制的ICP量子阱混杂技术

本文提出了一种针对InP/InGaAsP材料,基于空间控制技术的ICP量子阱混杂方法。同一片晶片上带隙能量的偏移程度可以通过掩膜上图形的不同占空比灵活的控制。通过一组优化的参数包括ICP-RIE刻蚀深度,二氧化硅沉积厚度,退火过程等,一个样品上,同时实现了五个不同的蓝移,其中最大的蓝移量达到75nm。结果显示在单片集成器件特别是多带隙结构器件的制作中这是一种有效的方法。     

多量子阱非对称法布里珀罗光调制器的模式波长调整

本文计算了不同折射率膜层下，非对称法布里珀罗腔模式波长随膜层厚度的变化．分析了在膜层折射率较低时，模式波长随层厚的增加反而减小的机理，并在实验中研究这种现象．利用湿法腐蚀的方法移动模式波长，补偿由生长误差引入的模式波长偏差，从而做到模式波长可控，获得高消光比的器件．同时利用湿法腐蚀方法将模式波长调整到不同位置，测量了不同模式波长位置时器件的调制特性     

二氧化硅覆盖退火增强磷化铟基体激光器材料的量子阱混合

我们对SiO2覆盖退火增强InGaAs/InGaAsP/InP激光器材料量子阱混合技术进行了实验研究.相对于原始样品,退火时无SiO2覆盖的样品经800℃,30s快速退火后,其光致发光谱的峰值波长“蓝移”了7nm,退火时有SiO2覆盖的样品经过同样的快速退火后,其光致发光谱的峰值波长“蓝移”了56nm.即在同一片子上实现了在需要量子阱混合的区域带隙的“蓝移”足够大的同时,不希望量子阱混合的区域能带结构的变化创记录的小.本文认为增大量子阱的宽度、采用无应力的量子阱结构以及引入足够厚的缓冲层可以改善量子阱材料的晶格质量,有利于提高量子阱混合技术的可靠性与重复性,     

半导体光集成电路

半导体光集成电路(PIC)是光电子集成电路(OEIC)的一个分支,它侧重于光学互连的导波光电子器件的单片集成。由于Ⅲ-Ⅴ族材料外延晶体生长和相关工艺技术方面的进步,这一研究领域最近取得明显进展。本文讨论了集成有源和无源光波导的某些必要技术,并介绍了几种典型器件。     

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AIGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

Optoelectronic smart pixels with hybrid integration of GaAs/AlGaAs multiple quantum well (MQW) detectors and modulators arrays have beed made,which are flip-chip bonded directly on the top of lμm silicon CMOS circuits,as enables an achievement of Optoelectronic Integrated Circuits (OEIC) as well as does the design and optimization of CMOS circuits and GaAs/AlGaAs MQW devices to proceed independently.     

国外光集成／光电集成技术的发展

ＰＩＣ／ＯＥＩＣ是实现长距离大容量光通信网、光用户网、光交换等关键器件。本文主要介绍了最近两年国外半导体材料技术、工艺技术的进展以及ＰＩＣ／ＯＥＩＣ器件的研制状况。     

OEIC台面腐蚀工艺研究

深入研究了牺牲层腐蚀机制,摸索出完整的台面自停止工艺并实际应用于OEIC器件制作。实验中发现了侧蚀、台面变形以及表面清洁等问题。从实验现象着手分析,并由此对工艺进行了改进,采用了新的腐蚀剂和工艺步骤。改进后的工艺解决了上述问题,可以完全满足后续工艺的要求。     

一种计算集成VDMOS管导通电阻的3D解析模型

功率集成电路要在同一块芯片上集成功率器件和低压电路。由于集成VDMOS器件的漏极也要从芯片表面引出,与常规的VDMOS器件相比其导通电阻计算有很大的差别。文中针对三维立体结构中器件的源胞个数和排列以及芯片表面漏极布局的不同,给出了一种新的3D解析模型,可有效地计算集成VDMOS的导通电阻值,并可预测限定面积下达到最小有效导通电阻值所需要的源胞个数和排列布局。     

Balanced operation of a GaInAs/GaInAsP multiple-quantum-wellintegrated heterodyne receiver

The balanced operation of a multiple-quantum-well balanced heterodyne receiver photonic integrated circuit (PIC) is described. Using only SMA-connected 50 Ω commercial electronics, a free-space beam sensitivity of -42.3 dBm at 108 Mb/s and -39.7 dBm at 200 Mb/s for NRZ FSK (frequency-shift keying) reception has been achieved. This represents a 14 dB improvement over any previous heterodyne receiver PIC sensitivity. In addition to providing the multichannel benefits of heterodyne reception, this is also the highest sensitivity yet reported for any OEIC (optoelectronic integrated circuit) receiver     

High-speed and energy-efficient subthreshold level converter for wider voltage conversion

Analog Integrated Circuits and Signal Processing - In this paper, a high speed and energy-efficient dynamic threshold MOSFET (DTMOS) based hybrid level converter (DTHLC) is proposed with wide...     

High-sensitivity BiCMOS OEIC for optical storage systems

A new BiCMOS optoelectronic integrated circuit (OEIC) for applications in advanced optical storage systems is presented. It is optimized with respect to high sensitivity and high speed. The photodiode and the amplifier are monolithically integrated on the same substrate in a commercial 0.8-/spl mu/m BiCMOS process. Analytical expressions for the compensation capacitors and for the bandwidth of the OEIC are derived. Neglecting antireflection coating, no process modifications are necessary to produce the integrated photodiodes. A new offset compensation scheme is implemented in the amplifiers to allow for a small chip area and low power consumption. The OEIC shows a sensitivity of 43.3 mV//spl mu/W in combination with a -3-dB bandwidth of 60.2 MHz.     

传送网络技术演进的思考

Driven by an ever-increasing number of new services and applications, transport networks have been undergoing significant changes. In this paper, we describe several exciting technology directions associated with future optical transport networks. We review the status of 100G, which is now commercially available and entering volume deployments, and its applications in China. Beyond 100G is considered as the primary technology for the expansion of both channel and fiber capacity in the near term, and several enabling techniques are introduced. Then, key technologies, products, and future evolutionary options of Optical Transport Networks (OTNs) are extensively discussed. Compared to fixed bandwidth and coarse granularity of current WDM network, a flexible grid architecture is a desirable evolu-tion trend, and key technologies and challenges are described. Finally, we illustrate the multi-dimension convergences in terms of IP and optical, Packet OTN (P-OTN), as well as Electronic Integrated Circuits (EICs) and Photonic Integrated Circuits (PICs). Transport networks are therefore in the process of be-coming more broadband, robust, flexible, cost-effective and lower-power-consumptive.     

Improvement of wider bandwidth using dual e–shaped antenna for wireless communications in 5G applications

Analog Integrated Circuits and Signal Processing - In this paper a dual E–shaped patch (ESP) antenna is proposed to enhance the wider impedance bandwidth to be use for wireless communications...     

Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell

Analog Integrated Circuits and Signal Processing - In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing...