A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at .

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Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

Calibration of Abstract Performance Models for System-Level Design Space Exploration

High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

Methods for Compression of Feedback in Adaptive Multi-carrier 4G Schemes

In this paper, several algorithms for compressing the feedback of channel quality information are presented and analyzed. These algorithms are developed for a proposed adaptive modulation scheme for future multi-carrier 4G mobile systems. These strategies compress the feedback data and, used together with opportunistic scheduling, drastically reduce the feedback data rate. Thus the adaptive modulation schemes become more suitable and efficient to be implemented in future mobile systems, increasing data throughput and overall system performance.

Capacity and SER Analysis of MIMO MRC Systems in an Interference-Limited Environment

The effect of co-channel interference (CCI) is considered in multiple-input multiple-output (MIMO) systems employing maximal ratio combining (MRC) under independent and identically distributed Rayleigh fading. Closed-form capacity and symbol error rate expressions are presented to evaluate the performance without any numerical integrations or statistical simulations. The analytical results are compared with Monte Carlo simulations and the good agreement is obtained.

Improved Fractional Fourier Transform Based Receiver for Spatial Multiplexed MIMO Antenna Systems

In this work the performance of a Fractional Fourier transform (FrFT) based Minimum Mean Squared Error receiver for MIMO systems with space time processing over Rayleigh faded channels is presented. The proposed receiver called Optimum FrFT based MIMO receiver (OFMR) shows improved performance outperforming the simple MMSE receiver in Rayleigh faded channel.

A feedback-based congestion control mechanism for labeled optical burst switched networks

In this article we describe a feedback-based OBS network architecture in which core nodes send messages to source nodes requesting them to reduce their transmission rate on congested links. Within this framework, we introduce a new congestion control mechanism called congestion control with explicit reduction request (CCERQ). Through feedback signals, CCERQ proactively attempts to prevent the network from entering the congestion state. Basic building blocks and performance tradeoffs of CCERQ are the main focus of this article.

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications

Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array elements in these loop nests has huge impact on the amount of memory required during execution. This is essential since the size and complexity of the memory hierarchy is the dominating factor for power, performance and chip size in these applications. This paper presents a number of guiding principles for the ordering of the dimensions in the loop nests. They enable the designer, or design tools, to find the optimal ordering of loop nest dimensions for individual data dependencies in the code. We prove the validity of the guiding principles when no prior restrictions are given regarding fixation of dimensions. If some dimensions are already fixed at given nest levels, this is taken into account when fixing the remaining dimensions. In most cases an optimal ordering is found for this situation as well. The guiding principles can be used in the early design phases in order to enable minimization of the memory requirement through in-place mapping. We use real life examples to show how they can be applied to reach a cost optimized end product. The results show orders of magnitude improvement in memory requirement compared to using the declared array sizes, and similar penalties for choosing the suboptimal ordering of loops when in-place mapping is exploited.

D-STAR MAC Protocol: A Cross Layer Solution for Wireless Sensor Networks Endowed with Directive Antennas

This paper deals with a novel MAC layer protocol, namely Directive synchronous transmission asynchronous reception (D-STAR), which is able to logically synchronize a Wireless sensor network (WSN). In this case both sleep and active states together with integrating directional antennas within the communications framework can be managed, according to a cross-layer design. D-STAR protocol has been characterized in terms of functional characteristics and the overall performance is presented in terms of network lifetime gain, set-up latency and collision probability. A remarkable gain is shown with respect to the basic approach endowed with omnidirectional antennas without increasing the signaling overhead nor affecting the set up latency, but achieving energy consumption reduction.

Reliability-aware Co-synthesis for Embedded Systems

As technology scales, transient faults have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability into hardware–software co-design paradigm for embedded systems. We introduce an allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded systems, and selectively duplicates critical tasks to detect or correct transient errors, such that the reliability of the system is improved. Two methods are proposed to insert duplicated tasks into the schedule. The improved reliability is achieved by utilizing the otherwise idle computation resources and taking advantage of the overlapping schedule for mutually exclusive tasks in the conditional task graph, such that it incurs no resource or performance penalty.

Performance Bound for LDPC Coded Unitary Space–Time Modulation

This paper is concerned with the bit error probability (BEP) of coded unitary space–time modulation systems based on finite-length low density parity check (LDPC) codes. The union bound on the BEP of the maximum likelihood (ML) decoding is derived for any code rate, unitary space–time constellation and mapping. The tightness of the bound is checked with simulation results of the ordered statistic decoding (OSD). Numerical and simulation results show that the union bound is also close to the error performance of the sum–product (SP) decoding at low BEP levels when Gray mapping is employed. The derived bound is useful to benchmark the error performance of finite-length coded unitary space–time modulation systems, especially for those that employ short-to-medium length LDPC codes.

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over \mathbbF2163 \mathbb{F}_{{2^{{163}} }} using Gaussian Normal Bases

This paper presents a comprehensive analysis of the design of custom instructions in a reconfigurable hardware platform dedicated to accelerate arithmetic operations in the binary field , using a Gaussian normal basis representation. The resulting platform is capable of running real applications, thus allowing a precise measurement of the execution overheads, and a fair comparison of the hardware and software speedups at several implementation levels. By using this approach, we determine which field operations (e.g., multiplication) are better suited to constrained environments, and which ones provide an enhanced performance in general-purpose systems. Experimental results reveal that by using our fastest field multiplier implemented as a custom instruction in a combined hardware/software approach, we accelerate point multiplication (the fundamental operation in Elliptic Curve Cryptography) over 126 times.

Strong practical stability and stabilization of discrete linear repetitive processes

This paper considers two-dimensional (2D) discrete linear systems recursive over the upper right quadrant described by well known state-space models. Included are discrete linear repetitive processes that evolve over subset of this quadrant. A stability theory exists for these processes based on a bounded-input bounded-output approach and there has also been work on the design of stabilizing control laws, elements of which have led to the assertion that this stability theory is too strong in many cases of applications interest. This paper develops so-called strong practical stability as an alternative in such cases. The analysis includes computationally efficient tests that lead directly to the design of stabilizing control laws, including the case when there is uncertainty associated with the process model. The results are illustrated by application to a linear model approximation of the dynamics of a metal rolling process.

A Joint OFDM Channel Estimation and ICI Cancellation for Double Selective Channels

Orthogonal frequency division multiplexing (OFDM) systems suffer significantly from inter-carrier interference (ICI) caused by double selective channels. In this paper, we develop a two-stage hybrid channel estimation and ICI cancellation structure for OFDM. The double selective channels are approximated by an improved Basis Expansion Model (BEM), which is more accurate than the conventional BEM when the normalized Doppler frequency is smaller than one. Based on this improved model, a new ICI cancellation scheme is proposed to reduce ICI impact. Simulation results show that the framework performs well.

Time-frequency hopping sequences with three no hit zones

Based on the idea of no hit zone (NHZ) in frequency hopping (FH) systems, new sequences with three no hit zones (T-NHZ) in time-frequency hopping (TFH) systems are presented. With the T-NHZ in the time- frequency (TF) correlation functions, the proposed T-NHZ sequences can be directly employed in time-frequency hopping code division multiple access (TFH-CDMA) communication systems to reduce or eliminate multipath interference. Simulation results show that T-NHZ sequences can achieve much better bit error performance than the NHZ sequences and the traditional FH sequences.

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a ‘grassfire’ transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomogeneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.

A Policy-based Approach for Reconfiguration Management and Enforcement in Autonomic Communication Systems

This paper presents an overview of the policy-based reconfiguration management and enforcement for autonomic communication system platform (Pre-meacs). In contrast to existing management approaches, which require static priori policy configurations, policies are created dynamically. The proposed Pre-meacs framework creates new policies at runtime in response to the changing requirements. A hierarchical policy model is used to refine users and administrators’ high-level goals into low-level objectives. The new approach ensures the success of the reconfiguration through monitoring feedback. The main components of Pre-meacs framework for policy creation, storage, evaluation and enforcement are presented, and the procedures of Pre-meacs in networks reconfiguration management are also demonstrated. Illustrative example demonstrates the performance of the proposed framework.

An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme.