An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.     

Fault simulation on massively parallel SIMD machines algorithms,implementations and results

Two algorithms for fault simulation of combinational networks on massively parallel SIMD machines are presented. One algorithm uses a variant of the PPSFP [1] approach, while the other uses a mixture of parallel fault simulation [2] and PPSFP [1]. The algorithms have been implemented on the [Thinking Machines Corporation's] Connection Machine [3]. The second algorithm compares very favorably with published results for well known serial algorithms on the ISCAS benchmark circuits [4]. The results indicate that parallel processing could be a valuable tool for accelerating VLSI CAD applications.     

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

基于指定元分析的多级相对微小故障诊断方法

 设备运作过程中可能出现的微小故障,往往会因其呈现的异常征兆较小而被淹没在显著故障或噪声中,从而现有的方法难以很好地对其进行监控.本文在DCA空间投影框架下建立了观测空间的多级分解思想,并在此基础上提出一种多级相对微小故障诊断算法.将观测数据关于显著指定模式进行DCA分析,并移除显著变化模式的影响,以提高微小故障信号的信噪比.根据其向故障子空间投影能量的显著性判断残差数据中是否还包含仍未被诊断出、且具有一定影响的微小故障;根据各故障方向上投影能量的显著性进行微小故障诊断;重复以上过程,直到各级微小故障均被诊断出来.包含四种共存故障的观测数据的仿真研究,验证了该算法的有效性.     

分级ad hoc网络中的一种应用层故障诊断算法

针对应用层故障提出了一种故障诊断算法——“基于簇的比较诊断算法”，该算法在分级ad hoc网络中利用簇首对簇内节点的集中控制功能优化了诊断过程，实现了诊断期问网络拓扑变化时对移动节点的诊断。证明了算法的正确性，并分析了算法的性能。仿真结果表明，该算法突破了“基于比较的故障诊断”在诊断过程中网络拓扑不能发生变化的限制，大大减小了“基于比较的故障诊断算法”由于诊断消息的洪泛导致的大量的系统开销。     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Parallel sequence fault simulation for synchronous sequential circuits

A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm successfully extend the parallel pattern method for combinational circuits to sequential circuits by proposing a multiple-pass mechanism to overcome the state dependency in sequential circuits. The fault simulation is performed in parallel by partitioning the entire sequence into subsequences of equal length. Furthermore, techniques are developed to minimize the number of simulation passes. Notably, two compact counters, C _x and C _d , are proposed to faciliate the early stabilization detection of faulty circuit simulation with minimum space overhead. The experimental results on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator based on ROOFS is 9.16 on average for pseudo random vectors. The parallel sequence algorithm of PSF is especially adaptable to parallel and distributed simulation which exploits sequence partition.     

Statistical estimation of delay fault detectabilities and fault grading

In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 1 and 1 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.     

Extended selection of switching target faults in CONT algorithm for test generation

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.     

变电站输电线路故障分析算法研究

提出了电力系统故障定位的重要性,选用一种原理简单,动作可靠的故障选相算法,在此基础上,综合多种定位算法的优点,结合故障分析系统的实际情况,采用阻抗法实现故障测距,并利用故障分量电流来消除过渡电阻的影响.     

WiNoC中无线通信拥塞与故障感知的容错路由算法

在无线片上网络中,无线通信拥塞和故障对整个片上网络的通信效率具有严重影响.为此本文提出了一种针对无线通信拥塞和故障的容错路由算法,首先设计了无线通信拥塞和故障感知模型,该模型能够感知无线节点通信对的拥塞和故障信息,并对其编码发送给子网中的路由器;然后子网中的路由器根据接收到的无线节点通信对状态信息,判断数据包是否使用无线传输.实验表明,本文方案相较于对比对象能够在较小的额外面积、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并对无线节点通信对的永久性故障具有良好的容错能力.     

应用数据融合实现电子电路的故障诊断

在电路故障诊断中,可通过直流分析、交流分析和灵敏度分析等方法,对电路的故障进行诊断.但由于不同的诊断方法对不同的故障敏感度不同,使得每种方法都带有局限性.为此,本文提出了采用数据融合进行电路故障诊断的新方法,介绍了D-S证据理论算法在电路故障诊断中的应用,给出了具体算法和仿真实例.理论分析和仿真结果表明,将数据融合技术用于电路的故障诊断是可行的.不同的诊断方法提供的信息经多次融合、反复抽取有用信息后,大大降低了判断的盲目性,提高了电路故障诊断的准确性.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

提高用任务重复的检查点方案的性能

设置检查点是减少程序在故障条件下执行时间的一种常用技术.将检查点与任务重复技术相结合,不仅能够完成有效的故障恢复,而且还能进行完善的故障检测.上述系统的开销主要来自两方面:其一是每个检查点的比较和保存开销,其二是因故障而引起的卷回.本文利用增量检查点对Ziv和Bruck提出的方法进行了改进,改进后的方法不仅能够有效地减少比较、保存检查点的开销,而且还能够避免潜伏故障引起的卷回.分析表明改进后的方法与Ziv和Bruck的方法相比表现出更好的性能.     

Selection of test paths for solder joint intermittent connection faults under DC stimulus

The test path of solder joint intermittent connection faults under direct-current stimulus is examined in this paper. According to the physical structure of the circuit, a network model is established first. A network node is utilised to represent the test node. The path edge refers to the number of intermittent connection faults in the path. Then, the selection criteria of the test path based on the node degree index are proposed and the solder joint intermittent connection faults are covered using fewer test paths. Finally, three circuits are selected to verify the method. To test if the intermittent fault is covered by the test paths, the intermittent fault is simulated by a switch. The results show that the proposed method can detect the solder joint intermittent connection fault using fewer test paths. Additionally, the number of detection steps is greatly reduced without compromising fault coverage.     

A survey on fault diagnosis of analog circuits: Taxonomy and state of the art

Due to the wide range of applications of electronic circuits in the recent years, the fault diagnosis in electronic circuits is a foremost problem. The main purpose of the fault diagnosis technique is isolating the faults present in the electronic circuits and also, detecting the fault which affects the safety and performance of the system. For various real-time applications of fault diagnosis, literature presents several techniques for detecting the faults in electronic circuits. In this paper, reviews on the research based on the fault diagnosis techniques which are all gained much attention are comprehended. Accordingly, 114 research papers related to the fault diagnosis are reviewed and analyzed based on the various objectives. In this review, we present the taxonomy of the fault detection in analog circuits and discuss the state of the art algorithms with various advantages and major drawbacks. The comprehensive analysis is carried out on finding the coverage of the publishers, faults, circuits, methods, simulation tools, and metrics. This critical review finally discusses the research challenges that are still available in the existing techniques and the way to extend the current research is also examined.     

基于边沿延时翻转的绑定前硅通孔测试方法

硅通孔（Through-Silicon Via,TSV）在制造过程中发生开路和短路等故障会严重影响3D芯片的可靠性和良率,因此对绑定前的TSV进行故障测试是十分必要的.现有的绑定前TSV测试方法仍存在故障覆盖不完全、面积开销大和测试时间大等问题.为解决这些问题,本文介绍一种基于边沿延时翻转的绑定前TSV测试技术.该方法主要测量物理缺陷导致硅通孔延时的变化量,并将上升沿和下降沿的延时分开测量以便消除二者的相互影响.首先,将上升沿延时变化量转化为对应宽度的脉冲信号;然后,通过脉宽缩减技术测量出该脉冲的宽度;最后,通过触发器的状态提取出测量结果并和无故障TSV参考值进行比较.实验结果表明,本文脉宽缩减测试方法在故障测量范围、面积开销等方面均有明显改善.